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21. 发明授权

US06785157B2 Semiconductor memory device having a memory cell structure of reduced occupying area 失效
标题翻译：具有占用面积减小的存储单元结构的半导体存储器件
公开(公告)号：US06785157B2
公开(公告)日：2004-08-31
申请号：US10119094
申请日：2002-04-10
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C1124
CPC分类号： G11C7/18 , G11C8/14 , G11C11/4085 , G11C11/4087 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108 , H01L27/1085 , H01L27/10873 , H01L27/10882
摘要： Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.
摘要翻译：构成存储单元板的导体线的导电线和构成存储单元板电极的导线被形成在包括多个存储单元的存储器件的同一互连层中，每个存储单元均包括用于以电荷形式存储数据的电容器。通过将存储单元的电容器形成为平面电容器配置，由于电容器而导致的步骤被去除。因此，可以通过CMOS工艺形成动态半导体存储器件，并且实现适合于与逻辑合并的动态半导体存储器件。 1位的数据由两个存储单元存储，即使由于平面型电容器而使存储单元的电容值减小，也可以可靠地存储数据。

22. 发明授权

US06636454B2 Low-power consumption semiconductor memory device 失效
公开(公告)号：US06636454B2
公开(公告)日：2003-10-21
申请号：US09756272
申请日：2001-01-09
申请人： Takeshi Fujino , Kazutami Arimoto , Hiroki Shimano
发明人： Takeshi Fujino , Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C700
CPC分类号： G11C11/4094 , G11C7/12
摘要： A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

23. 发明授权

US06573613B2 Semiconductor memory device having cell plate electrodes allowing independent power supply for each redundant replacement unit 有权
公开(公告)号：US06573613B2
公开(公告)日：2003-06-03
申请号：US10118433
申请日：2002-04-09
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： H01L27108
CPC分类号： G11C29/83 , G11C29/832 , H01L27/10897
摘要： A word line and a cell plate electrode line are formed at a common interconnection layer. A redundant replacement unit for a faulty row is set corresponding to the cell plate electrode line. For each redundant replacement unit, a program element is arranged for stopping supply of a cell plate voltage from the cell plate voltage line to the cell plate electrode line. The program element corresponding to the cell plate electrode line short-circuited to the word line nonvolatilely changes from the on state to the off state in response to an externally supplied input instruction.

24. 发明授权

US06545926B2 Antifuse address detecting circuit programmable by applying a high voltage and semiconductor integrated circuit device provided with the same 失效
标题翻译：防漏地址检测电路通过应用高电压和半导体集成电路器件可编程
公开(公告)号：US06545926B2
公开(公告)日：2003-04-08
申请号：US09197566
申请日：1998-11-23
申请人： Tsukasa Ooishi , Hiroki Shimano , Hideto Hidaka , Shigeki Tomishima
发明人： Tsukasa Ooishi , Hiroki Shimano , Hideto Hidaka , Shigeki Tomishima
IPC分类号： G11C700
CPC分类号： G11C29/70
摘要： An input protective circuit in a semiconductor integrated circuit device includes a bipolar transistor arranged for an interconnection layer. An N-type active region in the bipolar transistor is connected to an electrode of a program element. The electrode is connected to the interconnection layer. The interconnection layer supplies a high voltage for breaking a dielectric of a program element. A voltage on a P-type well is externally adjusted via a resistance element. Thereby, erroneous program due to serge entering at the interconnection layer can be avoided.
摘要翻译：半导体集成电路器件中的输入保护电路包括布置成互连层的双极晶体管。双极晶体管中的N型有源区连接到程序元件的电极。电极连接到互连层。互连层提供用于断开程序元件的电介质的高电压。通过电阻元件外部调整P型阱上的电压。因此，可以避免由于在互连层处进入的错误程序。

25. 发明授权

US06456560B2 Semiconductor integrated circuit device with test interface circuit for performing test on embedded memory from outside 失效
标题翻译：具有用于从外部对嵌入式存储器进行测试的测试接口电路的半导体集成电路器件
公开(公告)号：US06456560B2
公开(公告)日：2002-09-24
申请号：US09782286
申请日：2001-02-14
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C800
CPC分类号： G11C29/50012 , G11C11/401 , G11C29/14 , G11C29/48 , G11C29/50
摘要： A first test clock signal and a second test clock signal are generated from a common basic test clock signal using a delay line with a changeable delay time and a delay stage with a fixed delay time. A memory circuit is operated in synchronization with one of the first and second test clock signals, and the memory circuit is provided with a signal/data according to the other test clock signal. Thus, the set-up time and the hold time of a signal for the memory can be measured with accuracy in a memory-merged system LSI.
摘要翻译：使用具有可变延迟时间的延迟线和具有固定延迟时间的延迟级，从公共基本测试时钟信号产生第一测试时钟信号和第二测试时钟信号。存储器电路与第一和第二测试时钟信号中的一个同步地操作，并且根据另一个测试时钟信号向存储器电路提供信号/数据。因此，可以在存储器合并系统LSI中精确地测量存储器的信号的建立时间和保持时间。

26. 发明授权

US06388929B1 Semiconductor memory device performing redundancy repair based on operation test and semiconductor integrated circuit device having the same 失效
标题翻译：基于操作测试执行冗余修复的半导体存储器件和具有该半导体集成电路器件
公开(公告)号：US06388929B1
公开(公告)日：2002-05-14
申请号：US09906654
申请日：2001-07-18
申请人： Hiroki Shimano , Kazutami Arimoto
发明人： Hiroki Shimano , Kazutami Arimoto
IPC分类号： G11C2900
CPC分类号： G11C29/70 , G11C29/44
摘要： A BIST circuit conducts an operation test on a memory cell array to detect a defective memory cell when power is turned on. On the basis of a result of the operation test, the BIST circuit generates a redundancy code indicative of a defect address corresponding to a defective memory cell. The redundancy code is transmitted to a repair determining circuit in a decoding circuit. The repair determining circuit stores the redundancy code in a volatile manner during the power is on. When an input address coincides with the redundancy code to be stored on the inside, the repair determining circuit executes an access to a corresponding spare memory cell area.
摘要翻译： BIST电路在存储单元阵列上进行操作测试，以在电源接通时检测缺陷存储单元。基于操作测试的结果，BIST电路产生指示与缺陷存储单元对应的缺陷地址的冗余码。冗余码被传送到解码电路中的修复确定电路。修复确定电路在电源接通期间以易失性的方式存储冗余码。当输入地址与要存储在内部的冗余码一致时，修复确定电路执行对相应的备用存储单元区的访问。

27. 发明授权

US5023682A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5023682A
公开(公告)日：1991-06-11
申请号：US370662
申请日：1989-06-23
申请人： Masahiro Shimizu , Hiroki Shimano , Masahide Inuishi , Katsuhiro Tsukamoto
发明人： Masahiro Shimizu , Hiroki Shimano , Masahide Inuishi , Katsuhiro Tsukamoto
IPC分类号： H01L27/10 , G11C11/34 , H01L21/8242 , H01L27/00 , H01L27/108
CPC分类号： H01L27/10805
摘要： A semiconductor memory device comprises a p.sup.- -type semiconductor substrate (1), thin p.sup.+ -type regions (15, 80) formed thereon, n.sup.+ -type regions (6, 7) surrounded with the p.sup.+ -type regions (15, 80), a first gate electrode (2) formed on a charge storage region in the n.sup.+ -type region (6), and a second gate electrode (3) formed on the p.sup.+ -type region (80) and serving as a word line. The p.sup.+ -type regions (15, 80) prevent passage of electrons out of electron-hole pairs induced by alpha rays so as to prevent occurrence of soft errors. Advantageously, the thin p+ layer used to control threshold voltage for a transfer gate of the device is extended and also used for prevention of such soft errors, thus providing reduced bulk for the device. In order to reduce bulk further, the n+-type regions (6, 7) are also reduced in thickness. Films 16 and 17 are added to prevent an increase in diffusion resistance of the regions (6, 7) and the interconnection resistance of the second gate electrode (3). An oxide film (16) is formed on the side wall of the second gate electrode (3), a titanium silicide film (17) is formed on the n.sup.+ -type regions (6, 7) and a titanium silicide film (18) is formed on the second gate electrode (3) in a self-aligning manner.A bit line is formed on the semiconductor region and connected thereto. An interlayer insulation film is optionally formed between the bit line and the refractory metal silicide film placed on the semiconductor n.sup.+ -type region. The interlayer insulation film preferably comprises a silicon oxide film or a phosphorous oxide film. Finally, a protective film is optionally formed on the bit line. The protective film is preferably made of a material having a low dielectric constant.
摘要翻译：半导体存储器件包括p型半导体衬底（1），形成在其上的薄p +型区域（15,80），被p +型区域（15,80）包围的n +型区域（6,7），形成在n +型区域（6）的电荷存储区域上的第一栅电极（2）和形成在p +型区域（80）上并用作字线的第二栅电极（3）。 p +型区域（15,80）防止电子从α射线诱发的电子 - 空穴对中流出，以防止软错误的发生。有利地，用于控制装置的传输门的阈值电压的薄p +层被扩展，并且还用于防止这种软错误，从而为装置提供减少的体积。为了进一步减小体积，n +型区域（6,7）的厚度也减小。加入薄膜16和17以防止区域（6,7）的扩散阻力的增加和第二栅电极（3）的互连电阻的增加。在第二栅电极（3）的侧壁上形成氧化膜（16），在n +型区域（6,7）上形成硅化钛膜（17），硅化钛膜（18）为以自对准的方式形成在第二栅电极（3）上。在半导体区域上形成位线并与其连接。可选地，在位线和位于半导体n +型区域上的难熔金属硅化物膜之间形成层间绝缘膜。层间绝缘膜优选包含氧化硅膜或氧化磷膜。最后，可选地在位线上形成保护膜。保护膜优选由具有低介电常数的材料制成。

28. 发明授权

US4702797A Method of manufacturing semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US4702797A
公开(公告)日：1987-10-27
申请号：US943053
申请日：1986-12-18
申请人： Hiroki Shimano , Masahiro Shimizu , Katsuhiro Tsukamoto , Masahide Inuishi
发明人： Hiroki Shimano , Masahiro Shimizu , Katsuhiro Tsukamoto , Masahide Inuishi
IPC分类号： H01L27/10 , G11C11/34 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/08 , H01L29/10 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L27/1085 , H01L27/10805 , H01L29/0847 , H01L29/1083 , Y10S438/953
摘要： A method of manufacturing a semiconductor device comprises the steps of forming memory cell portions (2, 4, 6, 11) on a p.sup.- -type semiconductor substrate (1), forming a gate insulator film (5) and a gate electrode (3) each having a larger width, by approximately 1 .mu.m, than the original width, ion-implanting p-type impurities utilizing the gate insulator film (5) and the gate electrode (3) as masks, to form p.sup.+ -type regions (120, 121), etching the side walls of the gate insulator film (5) and the gate electrode (3) to the original width and then, ion-implanting n-type impurities utilizing these regions as a mask, to form n.sup.+ -type regions (80, 81), and heat-treating these regions (80, 81, 120, 121), to form regions (80a, 81a, 120a, 121a). The p.sup.+ -type regions (120a, 121a) prevent passage of electrons out of electron-hole pairs induced by alpha rays, to prevent occurrence of soft errors. The p.sup.+ -type regions (120a, 121a) are located inside the n.sup.+ -type regions (80a, 81a), so that operation of a parasitic pnp transistor is not caused.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在p型半导体衬底（1）上形成存储单元部分（2,4,6,11），形成栅极绝缘膜（5）和栅电极（3））各自具有比原始宽度大约1μm的离子注入p型杂质，利用栅极绝缘膜（5）和栅电极（3）作为掩模，形成p +型区域（将栅极绝缘体膜（5）和栅电极（3）的侧壁蚀刻到原始宽度，然后将这些区域的n型杂质离子注入作为掩模，形成n +型区域（80,81），并对这些区域（80,81,120,121）进行热处理，以形成区域（80a，81a，120a，121a）。 p +型区域（120a，121a）防止电子从由α射线诱发的电子 - 空穴对中流出，以防止发生软错误。 p +型区域（120a，121a）位于n +型区域（80a，81a）内部，从而不产生寄生pnp晶体管的操作。

29. 发明授权

US08971079B2 Inverter device 有权
标题翻译：变频器
公开(公告)号：US08971079B2
公开(公告)日：2015-03-03
申请号：US13638287
申请日：2011-03-31
申请人： Tetsuro Tateyama , Seiji Funaba , Yasuo Noto , Koichi Yahata , Hiroki Shimano
发明人： Tetsuro Tateyama , Seiji Funaba , Yasuo Noto , Koichi Yahata , Hiroki Shimano
IPC分类号： H02M3/24 , H02M7/5387
CPC分类号： H02M7/5387
摘要： An inverter device includes an inverter circuit, a control circuit, a first drive circuit, a second drive circuit, first and second photocouplers, and a signal switching part. The signal switching part directly transmits the first and second signals outputted from the first photocoupler and the second photocoupler to the corresponding first and second drive circuits respectively when at least one of the first and second signals is an OFF command.
摘要翻译：逆变器装置包括逆变器电路，控制电路，第一驱动电路，第二驱动电路，第一和第二光电耦合器以及信号切换部。当第一和第二信号中的至少一个是OFF命令时，信号切换部分分别将从第一光电耦合器和第二光电耦合器输出的第一和第二信号分别发送到对应的第一和第二驱动电路。

30. 发明授权

US08462251B2 Solid-state image sensor device and differential interface thereof 有权
标题翻译：固态图像传感器装置及其差分接口
公开(公告)号：US08462251B2
公开(公告)日：2013-06-11
申请号：US13542431
申请日：2012-07-05
申请人： Hiroki Shimano
发明人： Hiroki Shimano
IPC分类号： H04N5/335
CPC分类号： H04N5/3745 , H04N5/3577 , H04N5/3698 , H04N5/378
摘要： A solid-state image sensor device comprises an image sensor section for outputting analog signals of an image being taken; a plurality of AD converter sections, arranged with respect to the column direction of the image sensor section, for converting the analog signals into digital signals; a drive circuit section for controlling the image sensor section and the AD converter sections; and a plurality of differential interface sections for transmitting the digital signals converted by the AD converter sections as differential output signals to an external device. Each of the differential interface sections comprises a current value changeover circuit and offset voltage holding circuit operative when an operation mode changeover is made.
摘要翻译：固态图像传感器装置包括用于输出正在拍摄的图像的模拟信号的图像传感器部分; 多个AD转换器部分，相对于图像传感器部分的列方向布置，用于将模拟信号转换成数字信号; 用于控制图像传感器部分和AD转换器部分的驱动电路部分; 以及多个差分接口部分，用于将由AD转换器部分转换的数字信号作为差分输出信号发送到外部设备。每个差分接口部分包括当进行操作模式切换时可操作的电流值转换电路和失调电压保持电路。

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