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21. 发明申请

US20070217203A1 Lamp cooling device and rear projection display apparatus 失效
标题翻译：灯冷却装置和背投显示装置
公开(公告)号：US20070217203A1
公开(公告)日：2007-09-20
申请号：US11711646
申请日：2007-02-27
申请人： Hirokazu Ueda
发明人： Hirokazu Ueda
IPC分类号： F21V29/00
CPC分类号： H04N9/3144 , G03B21/10 , G03B21/145 , G03B21/16 , G03B21/28 , H04N9/3141
摘要： The present invention provides a lamp cooling device for cooling a lamp including a transparent front plate, a reflector that reflects light emitted from a light source to the transparent front plate, and the light-source disposed in an interior space enclosed by the transparent front plate and the reflector. The lamp cooling device includes a closed pipe line through which a gas is circulated. The lamp has a gas intake opening and a gas exhaust opening, the openings communicating with the interior space. The pipe line is connected to both of the gas intake opening and the gas exhaust opening so as to include the interior space of the lamp. The pipe line includes a flexible portion connected to the gas intake opening and another flexible portion connected to the gas exhaust opening.
摘要翻译：本发明提供了一种用于冷却灯的灯冷却装置，其包括透明前板，将从光源发射的光反射到透明前板的反射器，以及设置在由透明前板包围的内部空间中的光源和反射器。灯冷却装置包括气体循环通过的封闭管线。灯具有进气口和排气口，开口与内部空间连通。管道连接到气体进入口和排气口两者，以便包括灯的内部空间。管线包括连接到进气口的柔性部分和连接到排气口的另一柔性部分。

22. 发明授权

US07269091B2 Word line driver circuitry and methods for using the same 有权
标题翻译：字线驱动电路及使用方法
公开(公告)号：US07269091B2
公开(公告)日：2007-09-11
申请号：US10971939
申请日：2004-10-22
申请人： Hirokazu Ueda
发明人： Hirokazu Ueda
IPC分类号： G11C8/00 , G11C5/06 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4085 , G11C11/413
摘要： Word line driver circuitry for selectively charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology, where a first transistor is driven by a signal, DOUT, and a second transistor is driven by a time-delayed complement of the DOUT, DOUT_BAR. The time delay prevents DOUT_BAR from changing its state immediately after DOUT changes state. As result, both the first and second transistors are turned ON at the same time for a predetermined of time. It is during this time that the voltage on the word line is rapidly driven to a LOW voltage. When the second transistor turns OFF, high impedance circuitry limits the flow of leakage current. This minimizes leakage current when the word line is OFF and when short circuit conditions are present between two or more word lines or between a word line and a bit line.
摘要翻译：提供用于选择性地对一个或多个字线进行充电和放电的字线驱动器电路。驱动器电路使用双晶体管拓扑，其中第一晶体管由信号DOUT驱动，并且第二晶体管由DOUT DOUT_BAR的时间延迟的补码驱动。时间延迟可防止DOUT_BAR在DOUT更改状态后立即更改其状态。结果，第一和第二晶体管同时接通预定的时间。在这段时间内，字线上的电压被快速驱动到低电压。当第二个晶体管关断时，高阻抗电路会限制漏电流。当字线为OFF并且在两条或多条字线之间或字线与位线之间存在短路状况时，这将使漏电流最小化。

23. 发明授权

US07116596B2 Method of apparatus for enhanced sensing of low voltage memory 有权
标题翻译：低电压存储器增强感测装置的方法
公开(公告)号：US07116596B2
公开(公告)日：2006-10-03
申请号：US11038400
申请日：2005-01-19
申请人： Hirokazu Ueda
发明人： Hirokazu Ueda
IPC分类号： G11C7/02
CPC分类号： G11C7/065 , G11C2207/065
摘要： A differential sensing circuit and sensing method are provided for use in a low voltage memory device. The sensing circuit includes a cross-coupled sensing circuit for coupling with a memory element, a pull-up circuit and a multistage pull-down circuit. The multistage pull-down circuit accelerates the latching process of the cross-coupled sensing circuit by briefly pulling the cross-coupled sensing circuit to a potential below ground in order to increase the gate potential differential on at least a portion of the transistors within the cross-coupled sensing circuit. Once the latching transitions have commenced at an acceptable rate, the below-ground potential is removed and the traditional logic level pull-up and ground-potential pull-down circuits are activated.
摘要翻译：提供差分感测电路和感测方法用于低电压存储器件。感测电路包括用于与存储元件，上拉电路和多级下拉电路耦合的交叉耦合感测电路。多级下拉电路通过将交叉耦合的感测电路简单地拉到低于地电位的电位来加速交叉耦合的感测电路的锁存过程，以增加十字形内的晶体管的至少一部分上的栅极电位差耦合感测电路。一旦闭锁转换以可接受的速率开始，则地下电位被去除，传统的逻辑电平上拉电路和地电位下拉电路被激活。

24. 发明申请

US20050202648A1 Memory cells 有权
标题翻译：记忆单元
公开(公告)号：US20050202648A1
公开(公告)日：2005-09-15
申请号：US11119128
申请日：2005-04-29
申请人： Keiji Jono , Hirokazu Ueda , Hiroyuki Watanabe
发明人： Keiji Jono , Hirokazu Ueda , Hiroyuki Watanabe
IPC分类号： H01L21/762 , H01L21/8242 , H01L21/76
CPC分类号： H01L21/76232 , H01L27/10873
摘要： An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.
摘要翻译：半导体中的隔离沟槽包括具有第一深度并且具有以第一角度与半导体的表面相交的第一侧壁的第一隔离沟槽部分。第二隔离沟槽部分在第一隔离沟槽部分内和下方延伸。第二隔离沟槽部分具有第二深度并且包括第二侧壁。第二侧壁相对于大于第一角度的表面成一定角度与第一侧壁相交。电介质材料填充第一和第二隔离沟槽部分。

25. 发明授权

US06894354B2 Trench isolated transistors, trench isolation structures, memory cells, and DRAMs 有权
标题翻译：沟槽隔离晶体管，沟槽隔离结构，存储单元和DRAM
公开(公告)号：US06894354B2
公开(公告)日：2005-05-17
申请号：US10007300
申请日：2001-11-08
申请人： Keiji Jono , Hirokazu Ueda , Hiroyuki Watanabe
发明人： Keiji Jono , Hirokazu Ueda , Hiroyuki Watanabe
IPC分类号： H01L21/762 , H01L21/8242 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76232 , H01L27/10873
摘要： An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.
摘要翻译：半导体中的隔离沟槽包括具有第一深度并且具有以第一角度与半导体的表面相交的第一侧壁的第一隔离沟槽部分。第二隔离沟槽部分在第一隔离沟槽部分内和下方延伸。第二隔离沟槽部分具有第二深度并且包括第二侧壁。第二侧壁相对于大于第一角度的表面成一定角度与第一侧壁相交。电介质材料填充第一和第二隔离沟槽部分。

26. 发明授权

US06873559B2 Method and apparatus for enhanced sensing of low voltage memory 失效
公开(公告)号：US06873559B2
公开(公告)日：2005-03-29
申请号：US10345008
申请日：2003-01-13
申请人： Hirokazu Ueda
发明人： Hirokazu Ueda
IPC分类号： G11C11/409 , G11C7/06 , G11C7/00
CPC分类号： G11C7/065 , G11C2207/065
摘要： A differential sensing circuit and sensing method for use in a low voltage memory device. The sensing circuit includes a cross-coupled sensing circuit for coupling with a memory element, a pull-up circuit and a multistage pull-down circuit. The multistage pull-down circuit accelerates the latching process of the cross-coupled sensing circuit by briefly pulling the cross-coupled sensing circuit to a potential below ground in order to increase the gate potential differential on at least a portion of the transistors within the cross-coupled sensing circuit. Once the latching transitions have commenced at an acceptable rate, the below-ground potential is removed and the traditional logic level pull-up and ground-potential pull-down circuits are activated.

27. 发明申请

US20140051263A1 FILM FORMING METHOD 有权
标题翻译：电影制作方法
公开(公告)号：US20140051263A1
公开(公告)日：2014-02-20
申请号：US14113134
申请日：2012-04-23
申请人： Kouji Tanaka , Hirokazu Ueda
发明人： Kouji Tanaka , Hirokazu Ueda
IPC分类号： H01L21/316 , H01L21/318
CPC分类号： H01L21/316 , C23C16/345 , C23C16/4554 , C23C16/511 , H01L21/02164 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/318
摘要： This film forming method comprises: a first material gas supply step (A) wherein a first raw material gas is supplied over the substrate to be processed so that a first chemical adsorption layer, which is adsorbed on the substrate by means of the first raw material gas is formed on the substrate to be processed, a second material gas supply step (C) wherein a second raw material that is different from the first raw material gas is supplied over the substrate, on which the first chemical adsorption layer has been formed, so that a second chemical adsorption layer, which is adsorbed by means of the second raw material gas, is formed on the first chemical adsorption layer; and a plasma processing step (E) wherein a plasma processing is carried on at least the first and second chemical adsorption layers using microwave plasma.
摘要翻译：该成膜方法包括：第一原料气体供给工序（A），其中第一原料气体供给到被处理基板上，使得通过第一原料吸附在基板上的第一化学吸附层在被处理基板上形成气体，在其上形成有第一化学吸附层的基板上供给与第一原料气体不同的第二原料的第二原料气体供给工序（C）使得通过第二原料气体吸附的第二化学吸附层形成在第一化学吸附层上; 和等离子体处理步骤（E），其中至少使用微波等离子体对第一和第二化学吸附层进行等离子体处理。

28. 发明申请

US20130292700A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造半导体器件和半导体器件的方法
公开(公告)号：US20130292700A1
公开(公告)日：2013-11-07
申请号：US13981048
申请日：2012-01-23
申请人： Akinobu Teramoto , Hiroshi Kambayashi , Hirokazu Ueda , Yuichiro Morozumi , Katsushige Harada , Kazuhide Hasebe , Tadahiro Ohmi
发明人： Akinobu Teramoto , Hiroshi Kambayashi , Hirokazu Ueda , Yuichiro Morozumi , Katsushige Harada , Kazuhide Hasebe , Tadahiro Ohmi
IPC分类号： H01L29/20 , H01L21/02
CPC分类号： H01L21/02274 , H01L21/02164 , H01L21/02178 , H01L21/022 , H01L21/0228 , H01L21/0254 , H01L21/28264 , H01L23/564 , H01L29/2003 , H01L29/205 , H01L29/42364 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device including GaN (gallium nitride) that composes a semiconductor layer and includes forming a gate insulating film, in which at least one film selected from the group of a SiO2 film and an Al2O3 film is formed on a nitride layer containing GaN by using microwave plasma and the formed film is used as at least a part of the gate insulating film.
摘要翻译：一种制造半导体器件的方法，该半导体器件包括构成半导体层并包括形成栅极绝缘膜的GaN（氮化镓），其中在氮化物层上形成选自SiO 2膜和Al 2 O 3膜中的至少一种膜通过使用微波等离子体形成含GaN的GaN，并且将形成的膜用作栅极绝缘膜的至少一部分。

29. 发明申请

US20100075066A1 PLASMA FILM FORMING APPARATUS AND PLASMA FILM FORMING METHOD 审中-公开
标题翻译：等离子体膜形成装置和等离子体膜形成方法
公开(公告)号：US20100075066A1
公开(公告)日：2010-03-25
申请号：US12444600
申请日：2007-09-11
申请人： Hirokazu Ueda , Masahiro Horigome
发明人： Hirokazu Ueda , Masahiro Horigome
IPC分类号： C23C16/511 , C23C16/00
CPC分类号： C23C16/45565 , C23C16/402 , C23C16/4558 , C23C16/511 , H01J37/32192 , H01J37/32238 , H01J37/3244 , H01J37/32449 , H01J37/32623 , H01L21/31608
摘要： A plasma film forming apparatus includes: a processing chamber; a mounting table for mounting thereon a target object; a ceiling plate which is installed at a ceiling portion and is made of a dielectric material; a gas introduction mechanism for introducing a processing gas including a film formation source gas and a supporting gas; and a microwave introduction mechanism which is installed at a ceiling plate's side and has a planar antenna member. The gas introduction mechanism includes: a central gas injection hole for the source gas, located above a central portion of the target object; and a plurality of peripheral gas injection holes for the source gas, arranged above a peripheral portion of the target object along a circumferential direction thereof. A plasma shielding member is installed above the target object and between the central gas injection hole and the peripheral gas injection holes along the circumferential direction thereof.
摘要翻译：等离子体成膜装置包括：处理室; 用于安装目标物体的安装台; 天花板，其安装在顶部并由电介质材料制成; 用于引入包括成膜源气体和支持气体的处理气体的气体引入机构; 以及微波引入机构，其安装在天花板侧并具有平面天线构件。气体引入机构包括：位于目标物体的中心部分上方的用于源气体的中心气体注入孔; 以及多个用于原料气体的周边气体注入孔，沿着其圆周方向布置在目标物体的周边部分的上方。等离子体屏蔽部件沿着其周向方向安装在目标物体的上方，中央气体喷射孔和周边气体喷射孔之间。

30. 发明申请

US20090311872A1 GAS RING, APPARATUS FOR PROCESSING SEMICONDUCTOR SUBSTRATE, THE APPARATUS INCLUDING THE GAS RING, AND METHOD OF PROCESSING SEMICONDUCTOR SUBSTRATE BY USING THE APPARATUS 审中-公开
标题翻译：气体环，加工半导体基板的装置，包括气体环的装置以及使用装置处理半导体基板的方法
公开(公告)号：US20090311872A1
公开(公告)日：2009-12-17
申请号：US12483573
申请日：2009-06-12
申请人： Hirokazu UEDA , Yoshinobu TANAKA , Yasuhiro OTSUKA , Masanobu NAKAHASHI
发明人： Hirokazu UEDA , Yoshinobu TANAKA , Yasuhiro OTSUKA , Masanobu NAKAHASHI
IPC分类号： H01L21/465 , B05B1/14 , C23C16/455 , C23C16/511 , H01L21/46 , C23F1/08
CPC分类号： C23C16/4558
摘要： A gas ring has a ring shape and includes: a gas inlet hole through which a gas is introduced from outside the gas inlet hole into the gas ring; a plurality of gas jets that ejects the gas transferred from the gas inlet hole; and a plurality of branched paths extending along the ring shape from the gas inlet hole to each of the plurality of gas jets. Here, distances between each of the plurality of gas jets to central parts, which are branch points of each of the plurality of branched paths, are identical to each other.
摘要翻译：气环具有环状，并且包括：气体入口孔，气体从气体入口孔的外部引入气体环中; 喷射从气体导入孔传递的气体的多个气体射流; 以及沿着环状从气体入口孔延伸到多个气体射流中的多个分支路径。这里，作为多个分支路径中的每一个的分支点的多个气体喷射到中心部分的每个之间的距离彼此相同。

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