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21. 发明申请

US20100224885A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100224885A1
公开(公告)日：2010-09-09
申请号：US12715466
申请日：2010-03-02
申请人： Hidekatsu ONOSE
发明人： Hidekatsu ONOSE
IPC分类号： H01L29/24 , H01L27/06
CPC分类号： H01L29/8083 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0655 , H01L25/18 , H01L29/1608 , H01L29/66068 , H01L29/66909 , H01L2224/05599 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48237 , H01L2224/49 , H01L2224/73265 , H01L2224/85399 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01028 , H01L2924/01033 , H01L2924/014 , H01L2924/10253 , H01L2924/10272 , H01L2924/12032 , H01L2924/12036 , H01L2924/12041 , H01L2924/1306 , H01L2924/13062 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A semiconductor device having a junction FET having improved characteristics is provided. The semiconductor device has a junction FET as a main transistor and has a MISFET as a transistor for control. The junction FET has a first gate electrode, a first source electrode, and a first drain electrode. The MISFET has a second gate electrode, a second source electrode, and a second drain electrode. The MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET. The second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting. The first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.
摘要翻译：提供具有改善特性的结型FET的半导体器件。半导体器件具有作为主晶体管的结FET，并且具有MISFET作为用于控制的晶体管。结型FET具有第一栅电极，第一源电极和第一漏电极。 MISFET具有第二栅极电极，第二源极电极和第二漏极电极。 MISFET是n沟道型MISFET，具有增强型MISFET的电特性。 MISFET的第二栅电极和第二漏电极通过短路相互连接。结FET的第一栅电极和MISFET的第二源电极通过短路相互连接。

22. 发明申请

US20070114574A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070114574A1
公开(公告)日：2007-05-24
申请号：US11599356
申请日：2006-11-15
申请人： Hidekatsu Onose
发明人： Hidekatsu Onose
IPC分类号： H01L29/80
CPC分类号： H01L29/8083 , H01L29/1066 , H01L29/1608 , H01L29/41741 , H01L29/66068
摘要： An object of the present invention is to achieve both the high withstand voltage and the low on-resistance in a polycrystalline Si embedded gate SiC junction FET. n+ —SiC is formed as a drain layer; and n− —SiC which contacts an n+ drain layer is formed as a drift layer. By using n+ —SiC, which is formed on an n− drift layer, as a source layer, and by forming a trench from an n+ source layer up to a position having the specified depth of the n− drift layer, part of the n− drift layer is used as a channel region. As a result, in a junction FET including, as a gate region, p-type polycrystalline Si that is embedded in the trench, at least a side wall of the channel region contacts the p-type polycrystalline Si gate region without using oxidation film.
摘要翻译：本发明的目的是在多晶Si嵌入式栅极SiC结FET中实现高耐受电压和低导通电阻。 n + -SiC形成为漏极层; 并且与n +漏极层接触的n-SiC形成为漂移层。通过使用形成在n-漂移层上的n + -SiC作为源极层，并且通过形成从n +源层到具有n漂移层的指定深度的位置的沟槽，n - 漂移层用作通道区域。结果，在包括嵌入在沟槽中的p型多晶Si作为栅极区域的结型FET中，沟道区域的至少侧壁不使用氧化膜与p型多晶硅栅极区域接触。

23. 发明授权

US06940741B2 Semiconductor memory device and methods of operation thereof 失效
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US06940741B2
公开(公告)日：2005-09-06
申请号：US10807272
申请日：2004-03-24
申请人： Ryuichi Saito , Hidekatsu Onose , Yutaka Kobayashi , Michio Ohue
发明人： Ryuichi Saito , Hidekatsu Onose , Yutaka Kobayashi , Michio Ohue
IPC分类号： G11C14/00 , G11C11/22 , G11C11/56 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108 , H01L27/112 , H01L27/115 , G11C11/24
CPC分类号： H01L27/11502 , G11C8/14 , G11C11/22 , G11C11/5657 , G11C16/08 , H01L27/10805
摘要： A semiconductor memory device has a plurality of memory cells in an array, into which the memory cells data is writable, and which can subsequently be read. Each memory cell has a switching element with one terminal connected to a bit line of the array another terminal connected to at least one ferroelectric capacitor, and a control terminal connected to a word line. The cell may then be operated to detect the change in polarization of the ferroelectric capacitor when a voltage is applied which is not sufficient to cause a change of state of the ferroelectric capacitor. Alternatively, a ferroelectric capacitor and a capacitor other than a ferroelectric capacitor is connected to the switching element. In a further alternative, a plurality of ferroelectric capacitors are connected to the switching element, so that different data are writable into each.
摘要翻译：半导体存储器件具有阵列中的多个存储器单元，存储器单元数据可写入其中，并且随后可以读取存储单元。每个存储单元具有开关元件，一个端子连接到阵列的位线，另一个端子连接到至少一个铁电电容器，以及控制端子连接到字线。然后可以操作电池以在施加电压时检测铁电电容器的极化变化，这不足以引起铁电电容器的状态改变。或者，铁电电容器和除铁电电容器之外的电容器连接到开关元件。在另一替代方案中，多个铁电电容器连接到开关元件，使得不同的数据可写入每个。

24. 发明申请

US20110248286A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110248286A1
公开(公告)日：2011-10-13
申请号：US13082385
申请日：2011-04-07
申请人： Hidekatsu ONOSE
发明人： Hidekatsu ONOSE
IPC分类号： H01L29/24
CPC分类号： H01L29/861 , H01L21/26586 , H01L29/0878 , H01L29/1004 , H01L29/1066 , H01L29/1608 , H01L29/45 , H01L29/6606 , H01L29/66068 , H01L29/7302 , H01L29/7803 , H01L29/7813 , H01L29/8083
摘要： For suggesting a structure capable of achieving both a low start-up voltage and high breakdown voltage, a SiC vertical diode includes a cathode electrode, an n++ cathode layer, an n− drift layer on the n++ cathode layer, a pair of p+ regions, an n+ channel region formed between the n− drift layer and the p+ region and sandwiched between the pair of p+ regions, n++ anode regions and an anode electrode formed on the n++ anode regions and the p+ regions.
摘要翻译：为了提出能够实现低启动电压和高击穿电压的结构，SiC垂直二极管包括阴极电极，n ++阴极层，n ++阴极层上的n漂移层，一对p +区域， n +沟道区，形成在n-漂移层与p +区之间，夹在n + +阳极区和p +区之间的一对p +区，n + +阳极区域和阳极电极之间。

25. 发明申请

US20090032821A1 SEMICONDUCTOR DEVICE AND ELECTRICAL CIRCUIT DEVICE USING THEREOF 有权
标题翻译：使用其的半导体器件和电路装置
公开(公告)号：US20090032821A1
公开(公告)日：2009-02-05
申请号：US12179549
申请日：2008-07-24
申请人： Hidekatsu Onose , Hiroyuki Takazawa
发明人： Hidekatsu Onose , Hiroyuki Takazawa
IPC分类号： H01L29/78
CPC分类号： H01L29/7828 , H01L25/18 , H01L29/0623 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7391 , H01L2924/0002 , H01L2924/00
摘要： A UMOSFET is capable of reducing a threshold voltage and producing a large saturation current. A typical UMOSFET according to the present invention includes: an N+ type SiC substrate constituting a drain layer; an N− type SiC layer that is in contact with the drain layer and constitutes a drift layer; a P type body layer formed on the drift layer and being a semiconductor layer; an N+ type SiC layer constituting a source layer; a trench extending from the source layer to a predetermined location placed in the drift layer; a P type electric field relaxation region provided around and outside a bottom portion of the trench; and a channel region extending from the N+ type source layer to the P type electric field relaxation region and having an impurity concentration higher than that of the N− type drift layer and lower than that of the P type body layer.
摘要翻译： UMOSFET能够降低阈值电压并产生大的饱和电流。根据本发明的典型的UMOSFET包括：构成漏极层的N +型SiC衬底; 与漏极层接触并构成漂移层的N型SiC层; 形成在所述漂移层上并且是半导体层的P型体层; 构成源极层的N +型SiC层; 从源极层延伸到放置在漂移层中的预定位置的沟槽; 设置在沟槽的底部周围和外侧的P型电场弛豫区域; 以及从N +型源极层向P型电场弛豫区域延伸并且杂质浓度高于N型漂移层的杂质浓度并低于P型体层的沟道区域。

26. 发明申请

US20070252178A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070252178A1
公开(公告)日：2007-11-01
申请号：US11740728
申请日：2007-04-26
申请人： Hidekatsu ONOSE
发明人： Hidekatsu ONOSE
IPC分类号： H01L31/112
CPC分类号： H01L29/8083 , H01L29/0692 , H01L29/1608 , H01L29/66409 , H01L29/7722
摘要： The present invention can maintain a blocking state, even at a low gate bias voltage, in a diode-containing type of junction FET, and achieves a large saturation current.The junction FET includes: an n+ SiC substrate 10 as a drain layer; an n− SiC layer 11 contiguous to the drain layer as a drift layer; an n+ SiC layer 12 formed on the drift layer as a source layer; trench grooves formed ranging from the source layer to a required depth of the drift layer and part of the drift layer as a channel region; and p-type polycrystalline Si formed in the trench grooves as gate regions. The gate region at one side of the channel is electrically shorted to a source electrode to form a p− emitter of a diode.
摘要翻译：本发明即使在低二极管的类型的结型FET中也能保持低的栅极偏置电压下的阻塞状态，并且实现了大的饱和电流。结型FET包括：作为漏极层的n + S + SiC衬底10; 与漏极层邻接的n + SiC层11作为漂移层; 形成在漂移层上的作为源层的n + S + SiC层12; 从源极层到漂移层的所需深度和漂移层的一部分形成为沟道区的沟槽，以及形成在沟槽中的p型多晶Si作为栅极区。通道一侧的栅极区域与源电极电短路以形成二极管的p-O - 发射极。

27. 发明申请

US20070221994A1 Driver circuit for switching device 失效
标题翻译：开关装置的驱动电路
公开(公告)号：US20070221994A1
公开(公告)日：2007-09-27
申请号：US11657692
申请日：2007-01-25
申请人： Katsumi Ishikawa , Sunao Funakoshi , Kozo Sakamoto , Hidekatsu Onose
发明人： Katsumi Ishikawa , Sunao Funakoshi , Kozo Sakamoto , Hidekatsu Onose
IPC分类号： H01L23/62
CPC分类号： H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： A driver circuit that lowers the dependence of the loss in the wide gap semiconductor device upon the temperature is provided. A gate driver circuit for voltage driven power semiconductor switching device includes a power semiconductor switching device, a driver circuit for supplying a drive signal to a gate terminal of the switching device with reference to an emitter control terminal or a source control terminal of the switching device, and a unit for detecting a temperature of the switching device. The temperature of the power semiconductor switching device is detected, and a gate drive voltage or a gate drive resistance value is changed based on the detected temperature.
摘要翻译：提供了降低宽间隙半导体器件中的损耗对温度的依赖性的驱动电路。用于电压驱动的功率半导体开关器件的栅极驱动器电路包括功率半导体开关器件，驱动器电路，用于参照开关器件的发射极控制端子或源极控制端子向开关器件的栅极端子提供驱动信号，以及用于检测开关装置的温度的单元。检测功率半导体开关器件的温度，并且基于检测到的温度改变栅极驱动电压或栅极驱动电阻值。

28. 发明授权

US07256453B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07256453B2
公开(公告)日：2007-08-14
申请号：US11038929
申请日：2005-01-18
申请人： Hidekatsu Onose , Atsuo Watanabe
发明人： Hidekatsu Onose , Atsuo Watanabe
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/1066 , H01L29/7722 , H01L29/808
摘要： A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p+ gate and a gate electrode is formed on the bottom of the first region, the structure is built such that the p+ gate and an n+ source are contiguous. An insulating film is formed on the surface of an n− channel, and an auxiliary gate electrode is formed on the insulating film. In addition, the auxiliary gate electrode and the source electrode are shorted.
摘要翻译：提供了一种确保低导通电阻和更好的阻塞效果的结构。在其中第一区被用作栅极的横向型SIT（静态感应晶体管）中，并且栅极电极形成在第一区域的底部上，构造为使得p ^{+ 门和n ^{+ 源是连续的。在n通道的表面上形成绝缘膜，在绝缘膜上形成辅助栅电极。此外，辅助栅电极和源电极短路。}}

29. 发明申请

US20050218424A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050218424A1
公开(公告)日：2005-10-06
申请号：US11135417
申请日：2005-05-24
申请人： Hidekatsu Onose , Hideo Homma , Atsuo Watanabe
发明人： Hidekatsu Onose , Hideo Homma , Atsuo Watanabe
IPC分类号： H01L29/80 , H01L21/337 , H01L29/10 , H01L29/772 , H01L29/808 , H01L29/32
CPC分类号： H01L29/1066 , H01L29/1608 , H01L29/7722
摘要： A semiconductor switching device for an inverter includes a first conductivity type, low impurity concentration, semiconductor substrate having a band gap equal to or greater than 2.0 eV, a first conductivity type first region formed in a first plane of the substrate having a resistance lower than the substrate, a first electrode formed in another plane of the first region, a first conductivity type second region formed in a second plane of the substrate, and a second electrode formed on the second region. A trench is formed in the second plane, a control region is formed from a bottom of the trench into the substrate and a control electrode of a different conductivity type is formed on the control region. The second electrode is formed over the control electrode through an insulator film, and the control electrode is formed on the trench sidewalls so the control region contacts the second region.
摘要翻译：用于逆变器的半导体开关器件包括第一导电类型，低杂质浓度，具有等于或大于2.0eV的带隙的半导体衬底，形成在衬底的第一平面中的电阻低于所述基板，形成在所述第一区域的另一平面中的第一电极，形成在所述基板的第二平面中的第一导电类型的第二区域和形成在所述第二区域上的第二电极。在第二平面中形成沟槽，控制区域从沟槽的底部形成到衬底中，并且在控制区域上形成不同导电类型的控制电极。第二电极通过绝缘膜形成在控制电极上，并且控制电极形成在沟槽侧壁上，使得控制区域接触第二区域。

30. 发明申请

US20050121717A1 Semiconductor device 失效
公开(公告)号：US20050121717A1
公开(公告)日：2005-06-09
申请号：US11038929
申请日：2005-01-18
申请人： Hidekatsu Onose , Atsuo Watanabe
发明人： Hidekatsu Onose , Atsuo Watanabe
IPC分类号： H01L29/808 , H01L21/337 , H01L29/10 , H01L29/74 , H01L29/76 , H01L29/772 , H01L29/80 , H01L31/0256
CPC分类号： H01L29/1066 , H01L29/7722 , H01L29/808
摘要： A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p+ gate and a gate electrode is formed on the bottom of the first region, the structure is built such that the p+ gate and an n+ source are contiguous. An insulating film is formed on the surface of an n− channel, and an auxiliary gate electrode is formed on the insulating film. In addition, the auxiliary gate electrode and the source electrode are shorted.

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