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21. 发明申请

US20070164435A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070164435A1
公开(公告)日：2007-07-19
申请号：US11613914
申请日：2006-12-20
申请人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Fumiyuki Osanai
发明人： Kazutaka Koshiishi , Mitsuaki Katagiri , Satoshi Isa , Fumiyuki Osanai
IPC分类号： H01L23/52
CPC分类号： H01L23/66 , H01L23/49822 , H01L2224/48227 , H01L2224/49175 , H01L2924/19051 , H01L2924/3011 , H01L2924/3025 , H05K1/0216 , H05K1/024 , H05K3/4688 , H05K2201/09309 , H01L2924/00
摘要： To reduce noise between a power supply wiring and ground wiring especially in a small, high-density semiconductor device for high-speed operation. A semiconductor device having a second dielectric layer 5 made of dielectric material of which the dielectric loss tan 6 is at least 0.2 and interposed between a power supply wiring layer 6 electrically connected to a semiconductor chip and a ground wiring layer 4, so composed that a dielectric loss generated in the second dielectric layer 5 acts as a low pass filter of the power supply wiring layer 6, and having a first dielectric layer 3 made of dielectric material whose dielectric loss is less than the dielectric loss tan 6 of the second dielectric layer 5 and interposed between a signal wiring layer 2 electrically connected to the semiconductor chip and the ground wiring layer 4.
摘要翻译：为了降低电源布线和接地布线之间的噪音，特别是在高速运行的小型，高密度半导体器件中。一种半导体器件，具有由绝缘材料制成的介电损耗tanδ为0.2以上且介于与半导体芯片电连接的电源布线层6和接地布线层4之间的第二介质层5，在第二电介质层5中产生的介电损耗用作电源布线层6的低通滤波器，并且具有由介电损耗小于第二介电层的介电损耗tanδ的电介质材料制成的第一电介质层3 插入在与半导体芯片电连接的信号布线层2和接地布线层4之间。

22. 发明申请

US20060118937A1 Stacked-type semiconductor package 有权
标题翻译：堆叠型半导体封装
公开(公告)号：US20060118937A1
公开(公告)日：2006-06-08
申请号：US11291780
申请日：2005-12-02
申请人： Mitsuaki Katagiri , Atsushi Hiraishi , Fumiyuki Osanai
发明人： Mitsuaki Katagiri , Atsushi Hiraishi , Fumiyuki Osanai
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/3128 , H01L25/105 , H01L2224/50 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311
摘要： Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path.
摘要翻译：与第一半导体芯片的第一信号传输路径中的第一路径部分的对应部分是互连部件和第二路径部分，到第二半导体芯片的第二信号传输路径，并且不形成在第一条带上。允许第二信号传输路径的电长度独立于第一带被调整，使得第二信号传输路径的电长度可以容易地等于或基本等于第一信号传输路径的电长度。

23. 发明申请

US20120250264A1 MEMORY MODULE HAVING MEMORY CHIP AND REGISTER BUFFER 审中-公开
标题翻译：具有记忆芯片和寄存器缓冲存储器模块
公开(公告)号：US20120250264A1
公开(公告)日：2012-10-04
申请号：US13431498
申请日：2012-03-27
申请人： Fumiyuki OSANAI , Toshio SUGANO , Masayuki NAKAMURA
发明人： Fumiyuki OSANAI , Toshio SUGANO , Masayuki NAKAMURA
IPC分类号： H05K7/00
CPC分类号： G11C5/04
摘要： Disclosed herein is a memory module that includes a register buffer and a memory chip each mounted on a module substrate. Each of the command address output terminals belonging to the first group provided on the register buffer is connected to an associated one of the command address input terminals belonging to the first group provided on the memory chip through associated ones of the plurality of contact plugs and the first wiring layer. Each of the command address output terminals belonging to the second group provided on the register buffer is connected to an associated one of the command address input terminals belonging to the second group provided on the memory chip through associated ones of the plurality of contact plugs and the second wiring layer.
摘要翻译：这里公开了一种存储器模块，其包括每个安装在模块基板上的寄存器缓冲器和存储器芯片。属于设置在寄存器缓冲器上的第一组的命令地址输出端子中的每一个都通过多个接触插塞中的相关联的插头连接到属于存储器芯片上提供的第一组的命令地址输入端子中的一个，第一布线层。属于设置在寄存器缓冲器上的第二组的每个命令地址输出端子通过多个接触插头中的相关联的接头插头连接到属于存储器芯片上的第二组的命令地址输入端子中的一个，第二布线层。

24. 发明授权

US07994812B2 Calibration circuit, semiconductor device including the same, and data processing system 有权
标题翻译：校准电路，包括相同的半导体器件和数据处理系统
公开(公告)号：US07994812B2
公开(公告)日：2011-08-09
申请号：US12654253
申请日：2009-12-15
申请人： Fumiyuki Osanai , Hiroki Fujisawa
发明人： Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H03K17/16
CPC分类号： H03K19/0005
摘要： A semiconductor device adjusting an impedance level of an output buffer, includes a replica buffer circuit including a circuit configuration substantially identical to the output buffer, a counter circuit changing an impedance code to vary an impedance level of the replica buffer, a latch circuit temporarily holding the impedance code in response to a control signal, and an end-determining circuit producing the control signal in response to a lapse of a predetermined period from issuance of a calibration command, irrespective of a fact that the replica buffer has not yet reached a desirable impedance level.
摘要翻译：调整输出缓冲器的阻抗水平的半导体器件包括复制缓冲电路，其包括与输出缓冲器基本相同的电路配置，计数器电路改变阻抗代码以改变副本缓冲器的阻抗电平;锁存电路暂时保持响应于控制信号的阻抗代码，以及响应于从校准命令的发布而经过预定时间段而产生控制信号的终止确定电路，而不管复制缓冲器尚未达到期望的事实阻抗水平。

25. 发明授权

US07569428B2 Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same 有权
标题翻译：制造半导体器件的方法，半导体器件及包括该器件的器件
公开(公告)号：US07569428B2
公开(公告)日：2009-08-04
申请号：US11525952
申请日：2006-09-25
申请人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
发明人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H01L21/82 , H01L23/52
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.
摘要翻译：公开了一种制造半导体器件的方法的方法，该半导体器件包括衬底，半导体芯片和多个端子。该方法包括制备包括绝缘体的衬底，所述绝缘体形成有多条信号线，与多条信号线相关的多条电力线以及与该绝缘体上的多条信号线相关的多条地线，根据预定的布局。多个线路组中的每一个包括电力线中的一条，接地线中的一条和布置在一条电力线和一条接地线之间的一条信号线。所述多个线路组中的每一个与所述多个线路组中的相邻线路组共享所述电力线和接地线中的任何一个。

26. 发明申请

US20080224311A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080224311A1
公开(公告)日：2008-09-18
申请号：US12126681
申请日：2008-05-23
申请人： Satoshi ISA , Mitsuaki KATAGIRI , Fumiyuki OSANAI
发明人： Satoshi ISA , Mitsuaki KATAGIRI , Fumiyuki OSANAI
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L23/3114 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.
摘要翻译：公开了一种半导体器件，其包括数据族焊盘布局，其中努力设计电源引线和接地引线的布局，以将焊盘和焊球焊盘之间的引线的长度优先于最小化有效电感的半导体芯片。焊盘布局排列成两行，并且焊盘布局的一个单位被配置为使得数据电源和接地彼此相邻或者在数据电源和地之间插入一个数据。这样的配置减少数据电源之间的互感，并增加数据电源和地之间的互感，从而导致数据电源与地之间的有效电感的降低，从而导致功率和接地噪声的最小化。

27. 发明申请

US20080203584A1 Stacked-type semiconductor package 有权
标题翻译：堆叠型半导体封装
公开(公告)号：US20080203584A1
公开(公告)日：2008-08-28
申请号：US12081264
申请日：2008-04-14
申请人： Mitsuaki Katagiri , Atsushi Hiraishi , Fumiyuki Osanai
发明人： Mitsuaki Katagiri , Atsushi Hiraishi , Fumiyuki Osanai
IPC分类号： H01L25/065
CPC分类号： H01L25/0657 , H01L23/3128 , H01L25/105 , H01L2224/50 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311
摘要： Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path.
摘要翻译：与第一半导体芯片的第一信号传输路径中的第一路径部分的对应部分是互连部件和第二路径部分，到第二半导体芯片的第二信号传输路径，并且不形成在第一条带上。允许第二信号传输路径的电长度独立于第一带被调整，使得第二信号传输路径的电长度可以容易地等于或基本等于第一信号传输路径的电长度。

28. 发明申请

US20070273021A1 Semiconductor package 失效
标题翻译：半导体封装
公开(公告)号：US20070273021A1
公开(公告)日：2007-11-29
申请号：US11802888
申请日：2007-05-25
申请人： Fumiyuki Osanai , Atsushi Hiraishi , Toshio Sugano , Tsuyoshi Tomoyama , Satoshi Isa , Masahiro Yamaguchi , Masanori Shibamoto
发明人： Fumiyuki Osanai , Atsushi Hiraishi , Toshio Sugano , Tsuyoshi Tomoyama , Satoshi Isa , Masahiro Yamaguchi , Masanori Shibamoto
IPC分类号： H01L23/12
CPC分类号： H01L23/50 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/19041 , H01L2924/3011 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.
摘要翻译：半导体封装包括具有两个表面并且包括第一和第二电路径的衬底。在其中一个表面上安装了半导体芯片。半导体芯片包括多个焊盘，其包括要供应电源的第一焊盘和要接地的第二焊盘。在另一个表面上，安装至少一个旁路电容器。旁路电容器包括分别通过第一和第二电路连接到第一和第二焊盘的第一和第二端子。

29. 发明申请

US20070069362A1 Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same 有权
标题翻译：制造半导体器件的方法，半导体器件及包括该器件的器件
公开(公告)号：US20070069362A1
公开(公告)日：2007-03-29
申请号：US11525952
申请日：2006-09-25
申请人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
发明人： Satoshi Isa , Satoshi Itaya , Mitsuaki Katagiri , Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.
摘要翻译：公开了一种制造半导体器件的方法的方法，该半导体器件包括衬底，半导体芯片和多个端子。该方法包括制备包括绝缘体的衬底，所述绝缘体形成有多条信号线，与多条信号线相关的多条电力线以及与该绝缘体上的多条信号线相关的多条地线，根据预定的布局。多个线路组中的每一个包括电力线中的一条，接地线中的一条和布置在一条电力线和一条接地线之间的一条信号线。所述多个线路组中的每一个与所述多个线路组中的相邻线路组共享所述电力线和接地线中的任何一个。

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