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21. 发明申请

US20090321935A1 Methods of forming improved electromigration resistant copper films and structures formed thereby 审中-公开
标题翻译：形成改善的电迁移铜膜和由此形成的结构的方法
公开(公告)号：US20090321935A1
公开(公告)日：2009-12-31
申请号：US12215987
申请日：2008-06-30
申请人： Kevin O'Brien , Florian Gstrein , Sridhar Balakrishnan
发明人： Kevin O'Brien , Florian Gstrein , Sridhar Balakrishnan
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L23/53238 , H01L21/76843 , H01L21/76864 , H01L21/76877 , H01L21/76883 , H01L23/53223 , H01L23/53266 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a doping material on an overburden region of a conductive structure, diffusing a portion of the doping material into a portion of the conductive structure, and then removing the overburden region.
摘要翻译：描述了形成微电子结构的方法和相关结构。这些方法可以包括在导电结构的覆盖层区域上形成掺杂材料，将掺杂材料的一部分扩散到导电结构的一部分中，然后去除覆盖层区域。

22. 发明申请

US20090321934A1 SELF-ALIGNED CAP AND BARRIER 审中-公开
标题翻译：自对准的帽子和障碍物
公开(公告)号：US20090321934A1
公开(公告)日：2009-12-31
申请号：US12165016
申请日：2008-06-30
申请人： Adrien R. Lavoie , Florian Gstrein
发明人： Adrien R. Lavoie , Florian Gstrein
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76843 , H01L21/76849 , H01L21/76858 , H01L21/76867 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising an insulator layer formed on a substrate; a via formed by etching into the insulator layer to a first depth; a first metal layer formed over the insulator layer; a second metal layer deposited on the first metal layer to substantially fill the via; a metal-dopant alloy layer deposited over the second metal, wherein the dopant is diffused by annealing through the second metal layer and the first metal layer deposited in the via, such that the dopant migrates to a boundary between the first metal layer and the insulator to form a barrier; and an etch stop layer deposited over the via after planarization of the via and the insulator layer to form a barrier cap.
摘要翻译：一种半导体器件，包括形成在衬底上的绝缘体层; 通过将绝缘体层蚀刻到第一深度而形成的通孔; 形成在所述绝缘体层上的第一金属层; 沉积在第一金属层上以基本上填充通孔的第二金属层; 沉积在第二金属上的金属 - 掺杂剂合金层，其中掺杂剂通过退火通过第二金属层和沉积在通孔中的第一金属层而扩散，使得掺杂剂迁移到第一金属层和绝缘体之间的边界形成屏障; 以及在通孔和绝缘体层平坦化之后在通孔上沉积以形成阻挡盖的蚀刻停止层。

23. 发明申请

US20070292855A1 Method and CMOS-based device to analyze molecules and nanomaterials based on the electrical readout of specific binding events on functionalized electrodes 审中-公开
标题翻译：基于功能化电极上特异性结合事件的电气读出的方法和基于CMOS的器件来分析分子和纳米材料
公开(公告)号：US20070292855A1
公开(公告)日：2007-12-20
申请号：US11207000
申请日：2005-08-19
申请人： Valery Dubin , Florian Gstrein , Jonathan Lueker
发明人： Valery Dubin , Florian Gstrein , Jonathan Lueker
IPC分类号： C12Q1/68 , C12M3/00
CPC分类号： C12Q1/6816 , C12Q2565/607
摘要： A device having a functionalized electrode having a probe molecule, wherein the device has an ability to electrically detect a molecular binding event between the probe molecule and a target molecule by a polarization change of the functionalized electrode is disclosed. The device could also include an unfunctionalized electrode that does not have the probe molecule and the device could have an ability to electrically detect the molecular binding event between the probe molecule and the target molecule by a polarization change between the functionalized electrode and the unfuctionalized electrode.
摘要翻译：具有具有探针分子的官能化电极的器件，其中该器件具有通过官能化电极的偏振变化电探测探针分子与靶分子之间的分子结合事件的能力。该装置还可以包括不具有探针分子的未官能化电极，并且该装置可以具有通过功能化电极和未通电电极之间的偏振变化来电探测分子与靶分子之间的分子结合事件的能力。

24. 发明申请

US20070196575A1 Composite metal films and carbon nanotube fabrication 有权
标题翻译：复合金属薄膜和碳纳米管制作
公开(公告)号：US20070196575A1
公开(公告)日：2007-08-23
申请号：US11359165
申请日：2006-02-21
申请人： Juan Dominguez , Valery Dubin , Florian Gstrein , Michael Goldstein
发明人： Juan Dominguez , Valery Dubin , Florian Gstrein , Michael Goldstein
IPC分类号： C23C16/00 , C01B31/02
CPC分类号： B82Y40/00 , B82Y30/00 , C01B32/162 , Y10S977/742
摘要： Embodiments of the present invention provide methods for the fabrication of carbon nanotubes using composite metal films. A composite metal film is fabricated to provide uniform catalytic sites to facilitate the uniform growth of carbon nanotubes. Further embodiments provide embedded nanoparticles for carbon nanotube fabrication. Embodiments of the invention are capable of maintaining the integrity of the catalytic sites at temperatures used in carbon nanotube fabrication processes, 600 to 1100° C.
摘要翻译：本发明的实施例提供了使用复合金属膜制造碳纳米管的方法。制造复合金属膜以提供均匀的催化位点以促进碳纳米管的均匀生长。另外的实施方案提供用于碳纳米管制造的嵌入式纳米颗粒。本发明的实施方案能够在碳纳米管制造工艺中使用的温度下维持催化部位的完整性，其温度为600至1100℃

25. 发明申请

US20060275927A1 Method and apparatus to fabricate polymer arrays on patterned wafers using electrochemical synthesis 有权
公开(公告)号：US20060275927A1
公开(公告)日：2006-12-07
申请号：US11144679
申请日：2005-06-06
申请人： Valery Dubin , Florian Gstrein , Gordon Holt , Brandon Barnett
发明人： Valery Dubin , Florian Gstrein , Gordon Holt , Brandon Barnett
IPC分类号： H01L21/00 , H01L29/74
CPC分类号： B82Y30/00 , B01J19/0046 , B01J2219/00497 , B01J2219/005 , B01J2219/00527 , B01J2219/00574 , B01J2219/00576 , B01J2219/00585 , B01J2219/00596 , B01J2219/00653 , B01J2219/00659 , B01J2219/00662 , B01J2219/00675 , B01J2219/00677 , B01J2219/00689 , B01J2219/00713 , B01J2219/00722 , B01J2219/00725
摘要： A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.

26. 发明申请

US20150170961A1 SELECTIVE AREA DEPOSITION OF METAL FILMS BY ATOMIC LAYER DEPOSITION (ALD) AND CHEMICAL VAPOR DEPOSITION (CVD) 有权
标题翻译：通过原子层沉积（ALD）和化学气相沉积（CVD）的金属膜选择区沉积
公开(公告)号：US20150170961A1
公开(公告)日：2015-06-18
申请号：US14133262
申请日：2013-12-18
申请人： Patricio E. Romero , Scott B. Clendenning , Jeanette M. Roberts , Florian Gstrein
发明人： Patricio E. Romero , Scott B. Clendenning , Jeanette M. Roberts , Florian Gstrein
IPC分类号： H01L21/768
CPC分类号： H01L21/76897 , C23C16/04 , C23C16/18 , C23C16/45525 , H01L21/28506 , H01L21/28562 , H01L21/76801 , H01L21/76816 , H01L21/76838 , H01L21/76849 , H01L21/76879
摘要： Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.
摘要翻译：描述了通过原子层沉积（ALD）和化学气相沉积（CVD）来选择性地沉积金属膜。在一个示例中，制造用于集成电路的金属化结构的方法包括在衬底上形成暴露表面，暴露的表面包括暴露的介电材料的区域和暴露的金属的区域。该方法还涉及使用选择性金属沉积工艺在暴露的金属的区域上形成金属层，而不在暴露的电介质材料的区域上形成金属层。

27. 发明申请

US20140091467A1 FORMING BARRIER WALLS, CAPPING, OR ALLOYS /COMPOUNDS WITHIN METAL LINES 有权
标题翻译：在金属线中形成障碍物墙壁，吸收或合金/化合物
公开(公告)号：US20140091467A1
公开(公告)日：2014-04-03
申请号：US13630724
申请日：2012-09-28
申请人： Christopher J. Jezewski , Alan M. Meyers , Kanwal Jit Singh , Tejaswik K. Indukuri , James S. Clarke , Florian Gstrein
发明人： Christopher J. Jezewski , Alan M. Meyers , Kanwal Jit Singh , Tejaswik K. Indukuri , James S. Clarke , Florian Gstrein
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76808 , H01L21/76843 , H01L21/76847 , H01L21/76849 , H01L21/76883 , H01L21/76886 , H01L2924/0002 , H01L2924/00
摘要： Described herein are techniques structures related to forming barrier walls, capping, or alloys/compounds such as treating copper so that an alloy or compound is formed, to reduce electromigration (EM) and strengthen metal reliability which degrades as the length of the lines increases in integrated circuits.
摘要翻译：本文描述了与形成阻挡壁，封盖或合金/化合物相关的技术结构，例如处理铜以形成合金或化合物，以减少电迁移（EM）并增强金属可靠性，随着线的长度增加而降低集成电路。

28. 发明授权

US08278121B2 Method and apparatus to fabricate polymer arrays on patterned wafers using electrochemical synthesis 有权
标题翻译：使用电化学合成在图案化晶片上制造聚合物阵列的方法和装置
公开(公告)号：US08278121B2
公开(公告)日：2012-10-02
申请号：US13242127
申请日：2011-09-23
申请人： Valery M. Dubin , Florian Gstrein , Gordon D. Holt , Brandon Barnett
发明人： Valery M. Dubin , Florian Gstrein , Gordon D. Holt , Brandon Barnett
IPC分类号： H01L21/00
CPC分类号： B82Y30/00 , B01J19/0046 , B01J2219/00497 , B01J2219/005 , B01J2219/00527 , B01J2219/00574 , B01J2219/00576 , B01J2219/00585 , B01J2219/00596 , B01J2219/00653 , B01J2219/00659 , B01J2219/00662 , B01J2219/00675 , B01J2219/00677 , B01J2219/00689 , B01J2219/00713 , B01J2219/00722 , B01J2219/00725
摘要： A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
摘要翻译：具有在晶片上具有多个管芯（也称为阵列芯片）的晶片，该管芯具有产生脱保护试剂的电极，用于电化学合成材料的工作电极，邻近工作电极的约束电极以限制反应性试剂，以及管芯焊盘，其中，所述多个管芯的管芯焊盘在晶片上互连，以在多个工作电极上并行地电化学地合成所述材料。另外，公开了一种用于晶片尺寸制造多个管芯的方法和用于在晶片上的多个管芯上并行地电化学合成材料的方法。

29. 发明申请

US20120153483A1 BARRIERLESS SINGLE-PHASE INTERCONNECT 审中-公开
标题翻译：无障碍单相互连
公开(公告)号：US20120153483A1
公开(公告)日：2012-06-21
申请号：US12973281
申请日：2010-12-20
申请人： Rohan N. Akolkar , Florian Gstrein , Daniel J. Zierath
发明人： Rohan N. Akolkar , Florian Gstrein , Daniel J. Zierath
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/53261 , H01L21/3105 , H01L21/76825 , H01L21/76826 , H01L21/76877 , H01L21/76882 , H01L23/53247 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an interconnect structure and an integrated circuit including the interconnect structure. The method includes: depositing a dielectric layer over a conductive layer; forming an opening in the dielectric layer to expose the conductive layer; forming a barrierless single-phase interconnect comprising a metal or compound having a melting point between a melting point of copper and a melting point of tungsten. Forming includes depositing a layer of metal or compound within the opening and on an upper surface of the dielectric layer Preferably, the barrierless single-phase interconnect comprises cobalt or a cobalt containing compound. Thus, an interconnect structure, including a via and associated line, is made up of a single-phase metal or compound without the use of a different material between the interconnect and the underlying dielectric, thus improving electrical performance and reliability and further simplifying the interconnect formation process.
摘要翻译：形成互连结构的方法和包括所述互连结构的集成电路。该方法包括：在导电层上沉积介电层; 在所述电介质层中形成开口以暴露所述导电层; 形成包含熔点在铜的熔点和钨的熔点之间的金属或化合物的无障碍单相互连。形成包括在开口内和介电层的上表面上沉积一层金属或化合物。优选地，无障碍单相互连包括钴或含钴化合物。因此，包括通孔和相关线路的互连结构由单相金属或化合物构成，而不需要在互连和下面的电介质之间使用不同的材料，从而改善电性能和可靠性并进一步简化互连形成过程。

30. 发明授权

US07635503B2 Composite metal films and carbon nanotube fabrication 有权
标题翻译：复合金属薄膜和碳纳米管制作
公开(公告)号：US07635503B2
公开(公告)日：2009-12-22
申请号：US11359165
申请日：2006-02-21
申请人： Juan E. Dominguez , Valery M. Dubin , Florian Gstrein , Michael Goldstein
发明人： Juan E. Dominguez , Valery M. Dubin , Florian Gstrein , Michael Goldstein
IPC分类号： C23C16/00
CPC分类号： B82Y40/00 , B82Y30/00 , C01B32/162 , Y10S977/742
摘要： Embodiments of the present invention provide methods for the fabrication of carbon nanotubes using composite metal films. A composite metal film is fabricated to provide uniform catalytic sites to facilitate the uniform growth of carbon nanotubes. Further embodiments provide embedded nanoparticles for carbon nanotube fabrication. Embodiments of the invention are capable of maintaining the integrity of the catalytic sites at temperatures used in carbon nanotube fabrication processes, 600 to 1100° C.
摘要翻译：本发明的实施例提供了使用复合金属膜制造碳纳米管的方法。制造复合金属膜以提供均匀的催化位点以促进碳纳米管的均匀生长。另外的实施方案提供用于碳纳米管制造的嵌入式纳米颗粒。本发明的实施方案能够在碳纳米管制造工艺中使用的温度下维持催化部位的完整性，其温度为600至1100℃

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