专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20050199998A1 Semiconductor package with heat sink and method for fabricating the same and stiffener 审中-公开
标题翻译：具有散热器的半导体封装及其制造方法和加强件
公开(公告)号：US20050199998A1
公开(公告)日：2005-09-15
申请号：US10861544
申请日：2004-06-04
申请人： Chin-Te Chen , Wen-Che Lee , Chang-Fu Lin
发明人： Chin-Te Chen , Wen-Che Lee , Chang-Fu Lin
IPC分类号： H01L23/28
CPC分类号： H01L23/16 , H01L23/3128 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor package with a heat sink, a method for fabricating the same and a stiffener for the semiconductor package are proposed. At least one chip and the stiffener surrounding the chip are mounted on a substrate, and the heat sink is respectively attached to a non-active surface of the chip and the stiffener. A plurality of penetrating openings are formed on the stiffener, and an adhesive is filled in the penetrating openings to enhance the bonding strength of the heat sink and the stiffener, thereby inhibiting the heat sink and the stiffener from coming off.
摘要翻译：提出了具有散热器的半导体封装，其制造方法和半导体封装的加强件。至少一个芯片和围绕芯片的加强件安装在基板上，并且散热器分别附接到芯片和加强件的非活动表面。在加强件上形成有多个贯通孔，在贯通孔中填充有粘合剂，以增强散热器和加强件的接合强度，从而抑制散热器和加强件的脱落。

22. 发明申请

US20050168952A1 Semiconductor package 审中-公开
标题翻译：半导体封装
公开(公告)号：US20050168952A1
公开(公告)日：2005-08-04
申请号：US10974513
申请日：2004-10-26
申请人： Chin-Te Chen , Han-Ping Pu
发明人： Chin-Te Chen , Han-Ping Pu
IPC分类号： H01L23/04 , H01L23/10 , H05K7/20
CPC分类号： H01L23/04 , H01L23/10 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/16152 , H01L2924/16315
摘要： A semiconductor package includes a substrate; a chip mounted on a surface of the substrate; a lid having a flat portion and a support portion extending from the flat portion, wherein the support portion is attached to the substrate, with the chip being encompassed by the flat portion, the support portion and the substrate, and at least one cut-away portion is formed at an outer edge of a surface of the support portion attached to the substrate; an adhesive for attaching the lid to the substrate and filling the cut-away portion to allow an applied amount of the adhesive to be observed from the cut-away portion; and a plurality of solder balls mounted on another surface of the substrate. The applied amount of the adhesive can be adjusted optimally by provision of the cut-away portion to improve bonding strength between the lid and substrate and prevent flash of the adhesive.
摘要翻译：半导体封装包括基板; 安装在基板的表面上的芯片; 具有平坦部分和从所述平坦部分延伸的支撑部分的盖，其中所述支撑部分附接到所述基板，所述芯片被所述平坦部分，所述支撑部分和所述基板包围，并且至少一个切除部分形成在附着于基板的支撑部分的表面的外边缘处; 粘合剂，用于将盖子附接到基板并填充切除部分，以允许从切除部分观察涂布量的粘合剂; 以及安装在所述基板的另一表面上的多个焊球。可以通过设置切除部分来最佳地调节粘合剂的施加量，以提高盖和基板之间的粘合强度并防止粘合剂的闪光。

23. 发明申请

US20050056926A1 Heat dissipating structure and semiconductor package with the same 有权
标题翻译：散热结构和半导体封装相同
公开(公告)号：US20050056926A1
公开(公告)日：2005-03-17
申请号：US10851288
申请日：2004-05-21
申请人： Chin-Te Chen , Chang-Fu Lin
发明人： Chin-Te Chen , Chang-Fu Lin
IPC分类号： H01L23/10 , H01L23/36 , H01L23/495
CPC分类号： H01L23/10 , H01L23/36 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/16152 , H01L2924/16251 , H01L2924/163 , H01L2924/16315 , H01L2924/00
摘要： A heat dissipating structure and a semiconductor package with the same are proposed. A substrate is used to accommodate at least one chip thereon, and the chip is electrically connected to the substrate. A heat dissipating structure having a flat portion and a support portion is mount on the substrate via the support portion by means of an adhesive. At least one groove is formed on the support portion and at least one air vent is formed around the groove to allow the groove to communicate with the outside via the air vent, such that the adhesive is allowed to fill the groove to expel air from the groove to the atmosphere through the air vent, thereby preventing the air from trapped in the groove.
摘要翻译：提出了一种散热结构及其半导体封装。衬底用于容纳至少一个芯片，芯片电连接至衬底。具有平坦部分和支撑部分的散热结构通过粘合剂经由支撑部分安装在基板上。在支撑部分上形成至少一个凹槽，并且围绕凹槽形成至少一个排气孔，以允许凹槽经由排气口与外部连通，使得允许粘合剂填充凹槽以从空气中排出空气通过排气口到大气中，从而防止空气被捕获在槽中。

24. 发明申请

US20050036291A1 Semiconductor package with heat dissipating structure 有权
标题翻译：具有散热结构的半导体封装
公开(公告)号：US20050036291A1
公开(公告)日：2005-02-17
申请号：US10759863
申请日：2004-01-16
申请人： Chien-Ping Huang , Han-Ping Pu , Chin-Te Chen , Chang-Fu Lin
发明人： Chien-Ping Huang , Han-Ping Pu , Chin-Te Chen , Chang-Fu Lin
IPC分类号： H01L21/48 , H01L21/56 , H01L23/055 , H01L23/10 , H01L23/367 , H01L23/467 , H01L25/065 , H05K7/20
CPC分类号： H01L23/467 , H01L21/4882 , H01L21/563 , H01L23/055 , H01L23/10 , H01L23/3672 , H01L23/3675 , H01L25/0655 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73253 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/16315 , H01L2924/19105 , H01L2924/3011 , H01L2924/3511 , H01L2924/00
摘要： A semiconductor package with a heat dissipating structure includes a substrate, a chip and a heat dissipating structure. The chip is mounted on and electrically connected to the substrate. The heat dissipating structure includes a first heat sink having at least one positioning portion, and at least one second heat sink having at least one second positioning portion and at least one hollow portion. The second heat sink is mounted on the substrate, and the first positioning portion of the first heat sink is attached to the second positioning portion of the second heat sink, allowing the chip to be accommodated in a space defined by the first heat sink, the hollow portion of the second heat sink and the substrate. This semiconductor package has good heat dissipating efficiency and is cost-effective to fabricate.
摘要翻译：具有散热结构的半导体封装包括基板，芯片和散热结构。芯片安装在基板上并电连接到基板。散热结构包括具有至少一个定位部分的第一散热器和具有至少一个第二定位部分和至少一个中空部分的至少一个第二散热器。第二散热器安装在基板上，并且第一散热器的第一定位部分附接到第二散热器的第二定位部分，允许芯片容纳在由第一散热器限定的空间中，第二散热器的中空部分和基板。该半导体封装具有良好的散热效率，并且制造成本低。

25. 发明授权

US06703713B1 Window-type multi-chip semiconductor package 有权
标题翻译：窗型多芯片半导体封装
公开(公告)号：US06703713B1
公开(公告)日：2004-03-09
申请号：US10309478
申请日：2002-12-04
申请人： Wei-Cheng Tseng , Chin Te Chen
发明人： Wei-Cheng Tseng , Chin Te Chen
IPC分类号： H01L2350
CPC分类号： H01L25/0657 , H01L23/3114 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/06135 , H01L2224/06136 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48147 , H01L2224/4824 , H01L2224/48475 , H01L2224/49109 , H01L2224/4911 , H01L2224/85051 , H01L2225/0651 , H01L2225/06562 , H01L2225/06582 , H01L2225/06586 , H01L2924/01079 , H01L2924/014 , H01L2924/15311 , H01L2924/1579 , H01L2924/15798 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A window-type multi-chip semiconductor package is provided. A first chip and a second chip are mounted on a surface of a substrate formed with an opening, and a third chip is stacked on the first and second chips, wherein a plurality of bonding wires formed through the opening are used to electrically interconnect the chips and electrically connect the chips to the substrate. The chips are encapsulated by a first encapsulant formed on the surface of the substrate, and a second encapsulant is formed on an opposing surface of the substrate for encapsulating the bonding wires. With the chips being mounted on the same surface of the substrate, conductive elements such as bond pads formed on the chips are arranged toward the same direction and facilitate shortening of the bonding wires, thereby enhancing electrical transmission and performances for the semiconductor package.
摘要翻译：提供了一种窗型多芯片半导体封装。第一芯片和第二芯片安装在形成有开口的基板的表面上，并且第三芯片堆叠在第一和第二芯片上，其中通过开口形成的多个接合线用于将芯片并将芯片电连接到基板。芯片被形成在衬底表面上的第一密封剂封装，并且第二密封剂形成在衬底的相对表面上，用于封装接合线。利用芯片安装在基板的相同表面上，形成在芯片上的接合焊盘等导电元件朝向相同的方向排列，便于连接线的缩短，从而提高半导体封装的电气传输和性能。

26. 发明授权

US06670219B2 Method of fabricating a CDBGA package 有权
标题翻译：制造CDBGA封装的方法
公开(公告)号：US06670219B2
公开(公告)日：2003-12-30
申请号：US10310588
申请日：2002-12-04
申请人： Ming-Xun Lee , Chin-Te Chen
发明人： Ming-Xun Lee , Chin-Te Chen
IPC分类号： H01L2144
CPC分类号： H01L23/49816 , H01L23/3128 , H01L23/36 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48237 , H01L2224/49109 , H01L2224/73265 , H01L2924/00014 , H01L2924/01029 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/181 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A CDBGA package comprises a thermal dissipating substrate and a plurality of conductive bumps. A plurality of vias are formed on a circuit substrate and correspond to the conductive bumps. A plurality of ground pads, ball pads and nodes are formed on the circuit substrate, wherein the ground pads are located in the vias. A solder mask layer covers the patterned trace layer. A plurality of bonding pads are formed on a chip and are electrically connected to the nodes. A molding compound encapsulates the chip, nodes and bonding pads. A plurality of solder balls are located on the ground pads and ball pads, wherein the solder balls fill the vias and are electrically connected to the conductive bumps.
摘要翻译： CDBGA封装包括散热基板和多个导电凸块。多个通孔形成在电路基板上并对应于导电凸块。在电路基板上形成多个接地焊盘，球焊盘和节点，其中接地焊盘位于通孔中。焊接掩模层覆盖图案化的迹线层。多个接合焊盘形成在芯片上并与节点电连接。模塑料封装芯片，节点和焊盘。多个焊球位于接地焊盘和球焊盘上，其中焊球填充通孔并与导电凸块电连接。

27. 发明授权

US06441501B1 Wire-bonded semiconductor device with improved wire arrangement scheme for minimizing abnormal wire sweep 有权
标题翻译：具有改进的电线布置方案的线接半导体器件，用于最小化异常线扫
公开(公告)号：US06441501B1
公开(公告)日：2002-08-27
申请号：US09678184
申请日：2000-09-30
申请人： Charles Tseng , Chin-Te Chen , Yu-Ting Lai , Chung-Pao Wang
发明人： Charles Tseng , Chin-Te Chen , Yu-Ting Lai , Chung-Pao Wang
IPC分类号： H01L2352
CPC分类号： H01L24/85 , H01L21/565 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/05599 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/484 , H01L2224/49113 , H01L2224/4917 , H01L2224/49171 , H01L2224/49179 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01074 , H01L2924/14 , H01L2924/3025 , H01L2224/78 , H01L2224/45099 , H01L2924/00
摘要： A wire-bonded semiconductor device with an improved wire-arrangement scheme is proposed, which can help minimize abnormal wire sweep during encapsulation process. Among the bonding wires on the semiconductor device, those located in corners would be mostly susceptible to abnormal wire sweep, particularly a high-loop bonding wire that is located in immediate adjacency to a low-loop bonding wire located in one corner of the wire-bonded semiconductor device. To solve this problem, the low-loop bonding wire that is located in immediate adjacency to the sweep-susceptible high-loop bonding wire is erected substantially to the same loop height as the high-loop bonding wire, so that it can serve as a shield to the sweep-susceptible high-loop bonding wire against the flow of injected resin during encapsulation process, thus preventing abnormal wire sweep. Alternatively, if a pair of low-loop bonding wires are located in immediate adjacency to the sweep-susceptible high-loop bonding wire and are bonded to a common double-wire bond pad, these two low-loop bonding wires are arranged in an intercrossed manner, which can also help reduce the impact of the injected resin on the sweep-susceptible high-loop bonding wire, thus preventing abnormal wire sweep. The prevention of abnormal wire sweep allows the finished semiconductor device to be more assured in quality and reliability.
摘要翻译：提出了一种具有改进的布线方案的导线键合半导体器件，可以帮助最小化封装过程中的异常线扫。在半导体器件中的接合线之中，位于拐角处的那些将主要容易受到异常的线扫，特别是位于与位于线的一个拐角处的低环路接合线紧邻的高环路接合线，键合半导体器件。为了解决这个问题，位于与扫描敏感的高回路接合线直接相邻的低环路接合线基本上竖立成与高环接合线相同的环高度，从而可以作为在封装过程中屏蔽抗扫描敏感的高回路接合线，防止注入树脂的流动，从而防止异常的线扫。或者，如果一对低环路接合线立即与扫描敏感的高环路接合线相邻并且被结合到公共双线接合焊盘，则这两个低环路接合线布置在交叉方式，这也可以有助于减少喷射树脂对扫描敏感的高环接合线的影响，从而防止异常的线扫。防止异常线扫使得成品半导体器件在质量和可靠性方面更加放心。

28. 发明授权

US5507330A Workpiece feeding device for an edge shaping apparatus 失效
标题翻译：用于边缘成形设备的工件馈送装置
公开(公告)号：US5507330A
公开(公告)日：1996-04-16
申请号：US497221
申请日：1995-06-30
申请人： Chin-Te Chen
发明人： Chin-Te Chen
IPC分类号： B23Q3/00 , B23Q11/00 , B27C5/06 , B27B31/00
CPC分类号： B23Q3/002 , B23Q11/0046 , B27C5/06 , Y02P70/171
摘要： A workpiece feeding device is to be used with an edge shaping apparatus and includes a base unit, a housing unit, a feeding cylinder unit and a drive unit. The housing unit is mounted uprightly on the base unit and includes a surrounding wall with a front wall portion, and a partition member which is connected integrally to the surrounding wall and which cooperates with the front wall portion so as to confine a pair of upright cylindrical receiving spaces. The front wall portion is formed with a pair of vertical slots to access respectively the cylindrical receiving spaces. The feeding cylinder unit includes a pair of feeding cylinders received respectively in the cylindrical receiving spaces and mounted rotatably on the base unit. The feeding cylinders extend out of the cylindrical receiving spaces via the vertical slots. The drive unit is connected operably to the feeding cylinders and is operable so as to drive rotatably the feeding cylinders.
摘要翻译：工件供给装置与边缘成形装置一起使用，并且包括基座单元，壳体单元，进给缸单元和驱动单元。壳体单元垂直地安装在基座单元上，并且包括具有前壁部分的周围壁和分隔构件，该分隔构件一体地连接到周围壁并且与前壁部分配合，以限制一对直立的圆柱形接收空间。前壁部形成有一对垂直槽，以分别接近圆柱形接收空间。进料缸单元包括分别容纳在圆柱形容纳空间中并可旋转地安装在基座上的一对进料圆筒。进料缸通过垂直槽延伸出圆柱形接收空间。驱动单元可操作地连接到进料圆筒，并且可操作以可旋转地驱动进料圆筒。

29. 发明申请

US20100074438A1 SYSTEMS AND METHODS FOR KEY MANAGEMENT 审中-公开
标题翻译：关键管理系统与方法
公开(公告)号：US20100074438A1
公开(公告)日：2010-03-25
申请号：US12236971
申请日：2008-09-24
申请人： King-Hang WANG , Chin-Te Chen , Hung-Min Sun , Yih-Sien Kao
发明人： King-Hang WANG , Chin-Te Chen , Hung-Min Sun , Yih-Sien Kao
IPC分类号： H04L9/06 , H04L9/28 , H04N7/167
CPC分类号： H04L9/0836 , H04L9/0861 , H04L9/0891 , H04L9/3066 , H04L2209/601
摘要： A method for key management for a broadcasting system includes generating a receiver group key (RGK) seed and a plurality of parameters for a receiver group provided by the broadcasting system; and calculating an RGK for the receiver group based on the RGK seed and the plurality of parameters.
摘要翻译：一种用于广播系统的密钥管理的方法包括：生成由广播系统提供的接收机组的接收机组密钥（RGK）种子和多个参数; 以及基于所述RGK种子和所述多个参数来计算所述接收者组的RGK。

30. 发明申请

US20080230878A1 Leadframe based flip chip semiconductor package and lead frame thereof 审中-公开
标题翻译：基于引线框的倒装芯片半导体封装及其引线框架
公开(公告)号：US20080230878A1
公开(公告)日：2008-09-25
申请号：US12077489
申请日：2008-03-19
申请人： Wei-Lung Lu , Chih-Nan Lin , Shih-Kuang Chiu , Chin-Te Chen
发明人： Wei-Lung Lu , Chih-Nan Lin , Shih-Kuang Chiu , Chin-Te Chen
IPC分类号： H01L23/495
CPC分类号： H01L23/4951 , H01L23/3107 , H01L23/49541 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： A flip chip semiconductor package is disclosed according to the present invention, the flip chip semiconductor package comprises a chip that is mounted on and electrically connects to a leadframe via a plurality of solder bumps by means of flip chip, and an encapsulate that encapsulates the chip, the plurality of solder bumps, and the leadframe, wherein, the leadframe further comprises a plurality of leads and a ground plane that is located between the plurality of leads, and also a slit is formed on the ground plane, and then a molding compound that makes up the encapsulant should be capable of filling within the slit, thus to enhance the adhesion between the ground plane and the encapsulant, and then avoid delamination between the ground plane and the encapsulant in subsequent thermal cycle processes, thereby increasing the reliability of fabricated products.
摘要翻译：根据本发明公开了一种倒装芯片半导体封装，所述倒装芯片半导体封装包括通过倒装芯片经由多个焊料凸块安装在引线框架上并与其电连接的芯片，以及封装芯片多个焊料凸块和引线框架，其中引线框还包括多个引线和位于多个引线之间的接地平面，并且在接地平面上形成狭缝，然后形成模塑料这样构成的密封剂应该能够在狭缝内填充，从而增强接地层与密封剂之间的密合性，然后避免在随后的热循环过程中接地层与密封剂之间的分层，从而提高制造的可靠性产品。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式