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    • 26. 发明申请
    • METHODOLOGY TO GUARD ESD PROTECTION CIRCUITS AGAINST PRECHARGE EFFECTS
    • 防止预防效应的ESD保护电路的方法
    • US20100226056A1
    • 2010-09-09
    • US12783240
    • 2010-05-19
    • Chih-Ming HungCharvaka Duvvury
    • Chih-Ming HungCharvaka Duvvury
    • H02H9/04
    • H02H9/046
    • An ESD protection circuit (710) is guarded by a parallel first precharge elimination circuit (720) relative to an I/O pad (721) and a parallel second precharge elimination circuit (730) relative to a VDD pad (731). The precharge elimination circuits are synchronized with the ESD protection circuit to eliminate any precharge voltage to ground before an ESD pulse affects the I/O pad or VDD pad. A diode (722) is connected between I/O pad and VDD. Circuit (720) is between I/O pad and ground (740) and is powered by the same VDD. Circuit (720) includes a first resistor (723), a first nMOS transistor (724), and a first RC timer including a second resistor (725) and a first capacitor (726). Circuit (730) includes a third resistor (733), a second nMOS transistor (734), and a second RC timer including a fourth resistor (735) and a second capacitor (736).
    • ESD保护电路(710)相对于VDD焊盘(731)相对于I / O焊盘(721)和并行的第二预充电消除电路(730)由并行的第一预充电消除电路(720)保护。 预充电消除电路与ESD保护电路同步,以在ESD脉冲影响I / O焊盘或VDD焊盘之前消除任何对地的预充电电压。 二极管(722)连接在I / O焊盘和VDD之间。 电路(720)位于I / O焊盘和接地(740)之间,由相同的VDD供电。 电路(720)包括第一电阻器(723),第一nMOS晶体管(724)和包括第二电阻器(725)和第一电容器(726)的第一RC定时器。 电路(730)包括第三电阻器(733),第二nMOS晶体管(734)和包括第四电阻器(735)和第二电容器(736)的第二RC定时器。
    • 29. 发明授权
    • Low noise high isolation transmit buffer gain control mechanism
    • 低噪声高隔离传输缓冲器增益控制机制
    • US07463869B2
    • 2008-12-09
    • US11115815
    • 2005-04-26
    • Chih-Ming HungFrancis P. CruiseDirk LeipoldRobert B. Staszewski
    • Chih-Ming HungFrancis P. CruiseDirk LeipoldRobert B. Staszewski
    • H04B1/04
    • H04B1/0483H03F1/3241H03F1/3294H03F3/191H03F2200/331
    • A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high. The significant on resistance of the NMOS switches is exploited in the DRAC circuit to introduce power control of the transmitted waveform and permits a fully digital method of controlling the RF output power.
    • 一种低噪声,高隔离,全数字发送缓冲增益控制机制的新型设备。 增益控制方案在全数字直接数/频幅度转换器(DRAC)的上下文中呈现,该转换器有效地结合了上变频,I和Q组合,D / A转换,滤波,缓冲和 RF输出幅度控制成单个电路。 发送缓冲器构造为NMOS开关阵列。 每个NMOS开关的控制逻辑包括一个通门型AND门,其输入是全数字PLL的相位调制输出和来自数字控制块的幅度控制字。 通过在CMOS工艺中实现时,通过识别伪E类预功率放大器(PPA)所遭受的损伤来实现功率控制。 首先,阵列的NMOS开关具有大的导通电阻,因此当输入波形为高时,只能从RF扼流圈画出有限的电流。 在DRAC电路中利用NMOS开关的重要导通电阻来引入发射波形的功率控制,并允许控制RF输出功率的全数字方法。