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21. 发明授权

US08037432B2 Method and apparatus for mapping design memories to integrated circuit layout 有权
标题翻译：将设计存储器映射到集成电路布局的方法和装置
公开(公告)号：US08037432B2
公开(公告)日：2011-10-11
申请号：US12186159
申请日：2008-08-05
申请人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/025
摘要： A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.
摘要翻译：提供了一种用于接收设计存储器列表的方法和装置，其中列表中的每种类型的设计存储器具有名称和至少一个实例。预置位模型与列表中的每个命名存储器类型相关联。列表中的设计存储器被映射到集成电路布局模式，其中至少一个存储器类型包括彼此不同地映射的第一和第二实例。映射后，第一个和第二个实例中的至少一个被重命名为具有与另一个不同的名称。然后，后置放置模型与列表中的每个命名存储器类型相关联，包括每个重命名的设计存储器的单独模型。

22. 发明申请

US20090307543A1 TRANSPORT SUBSYSTEM FOR AN MBIST CHAIN ARCHITECTURE 失效
标题翻译：用于MBIST链架构的运输子系统
公开(公告)号：US20090307543A1
公开(公告)日：2009-12-10
申请号：US12183512
申请日：2008-07-31
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/26 , G11C29/32 , G11C2029/2602 , G11C2029/5602
摘要： An apparatus comprising a controller, a plurality of transport circuits and a plurality of memory-controlling circuits. The controller may be configured to (i) present one or more commands and (ii) receive one or more responses. Each of the plurality of transport circuits may be configured to (i) receive one of the commands, (ii) present the responses, and (iii) generate one or more control signals. Each of the plurality of memory-controlling circuits may be (i) coupled to a respective one of the plurality of transport circuits and (ii) configured to (i) generate one or more memory access signals in response to the one or more control signals, (ii) receive one or more memory output signals from a respective memory in response to the one or more memory access signals and (iii) generate the responses in response to the one or more memory output signals. Each respective memory may be independently sized. The controller generally provides a common testing routine for each respective memory that may be adjusted for the size of each respective memory by the memory-controlling circuits.
摘要翻译：一种装置，包括控制器，多个传输电路和多个存储器控制电路。控制器可以被配置为（i）呈现一个或多个命令，并且（ii）接收一个或多个响应。多个传输电路中的每一个可以被配置为（i）接收命令之一，（ii）呈现响应，以及（iii）产生一个或多个控制信号。多个存储器控制电路中的每一个可以（i）耦合到多个传输电路中的相应一个，并且（ii）被配置为（i）响应于一个或多个控制信号而产生一个或多个存储器访问信号，（ii）响应于所述一个或多个存储器访问信号，从相应存储器接收一个或多个存储器输出信号，以及（iii）响应于所述一个或多个存储器输出信号产生响应。各个存储器可以独立地定尺寸。控制器通常为每个相应的存储器提供通用的测试程序，这些存储器可以通过存储器控制电路为每个相应的存储器的大小进行调整。

23. 发明申请

US20090300440A1 DATA CONTROLLING IN THE MBIST CHAIN ARCHITECTURE 失效
标题翻译：在MBIST链架构中的数据控制
公开(公告)号：US20090300440A1
公开(公告)日：2009-12-03
申请号：US12167305
申请日：2008-07-03
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/04 , G06F11/27
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences.
摘要翻译：一种包括第一电路和第二电路的存储器环。第一电路可以被配置为响应于一个或多个测试命令而生成一个或多个数据序列。在测试模式期间，可以将一个或多个数据序列呈现给存储器。第二电路可以被配置为响应于一个或多个数据序列预处理由存储器产生的一个或多个输出。

24. 发明申请

US20090282303A1 BUILT IN TEST CONTROLLER WITH A DOWNLOADABLE TESTING PROGRAM 有权
标题翻译：用可测试的测试程序构建测试控制器
公开(公告)号：US20090282303A1
公开(公告)日：2009-11-12
申请号：US12118477
申请日：2008-05-09
申请人： Alexandre Andreev , Anatoli A. Bolotov
发明人： Alexandre Andreev , Anatoli A. Bolotov
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G11C5/04 , G11C29/16 , G11C2029/0401
摘要： An apparatus comprising a processor and an internal memory. The processor may be configured to test an external memory using (i) a netlist and (ii) a testing program. The internal memory may be configured to store the testing program. The testing program may be downloadable to the internal memory independently from the storing of the netlist.
摘要翻译：一种包括处理器和内部存储器的装置。处理器可以被配置为使用（i）网表和（ii）测试程序来测试外部存储器。内部存储器可以被配置为存储测试程序。测试程序可以独立于存储网表而被下载到内部存储器。

25. 发明申请

US20070136704A1 Method and apparatus for generating memory models and timing database 失效
标题翻译：用于生成内存模型和计时数据库的方法和装置
公开(公告)号：US20070136704A1
公开(公告)日：2007-06-14
申请号：US11298894
申请日：2005-12-09
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种用于创建和使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

26. 发明授权

US08245168B2 Method and apparatus for generating memory models and timing database 失效
标题翻译：用于生成内存模型和计时数据库的方法和装置
公开(公告)号：US08245168B2
公开(公告)日：2012-08-14
申请号：US12508320
申请日：2009-07-23
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种用于创建和使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

27. 发明授权

US08209589B2 Reed-solomon decoder with a variable number of correctable errors 失效
标题翻译： Reed-solomon解码器具有可变数量的可纠正错误
公开(公告)号：US08209589B2
公开(公告)日：2012-06-26
申请号：US12212022
申请日：2008-09-17
申请人： Alexandre Andreev , Ilya Neznanov , Elyar Gasanov , Pavel Panteleev
发明人： Alexandre Andreev , Ilya Neznanov , Elyar Gasanov , Pavel Panteleev
IPC分类号： H03M13/00
CPC分类号： H03M13/1515 , H03M13/159 , H03M13/6516
摘要： A syndrome calculator receives an input codeword and calculates a first set of syndromes. A syndrome transform receives the first set of syndromes having and determines a second set of syndromes. The second set of syndromes is based on the first set of syndromes. The second set of syndromes has number of syndromes that is less than the number of syndromes in the first set of syndromes. A key equation solver receives the second set of syndromes and produces an indication of zero or more error locations and an indication of zero or more error values.
摘要翻译：校正子计算器接收输入码字并计算第一组综合征。综合征变换接收具有并确定第二组综合征的第一组综合征。第二组综合征是基于第一组综合征。第二组综合征的综合征数量少于第一组综合征中的综合征数。关键方程求解器接收第二组综合征，并产生零个或多个错误位置的指示以及零个或多个误差值的指示。

28. 发明申请

US20100070832A1 REED-SOLOMON DECODER WITH A VARIABLE NUMBER OF CORRECTABLE ERRORS 失效
标题翻译： REED-SOLOMON解码器具有可变数量的可纠正错误
公开(公告)号：US20100070832A1
公开(公告)日：2010-03-18
申请号：US12212022
申请日：2008-09-17
申请人： Alexandre Andreev , Ilya Neznanov , Elyar Gasanov , Pavel Panteleev
发明人： Alexandre Andreev , Ilya Neznanov , Elyar Gasanov , Pavel Panteleev
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： H03M13/1515 , H03M13/159 , H03M13/6516
摘要： A syndrome calculator receives an input codeword and calculates a first set of syndromes. A syndrome transform receives the first set of syndromes having and determines a second set of syndromes. The second set of syndromes is based on the first set of syndromes. The second set of syndromes has number of syndromes that is less than the number of syndromes in the first set of syndromes. A key equation solver receives the second set of syndromes and produces an indication of zero or more error locations and an indication of zero or more error values.
摘要翻译：校正子计算器接收输入码字并计算第一组综合征。综合征变换接收具有并确定第二组综合征的第一组综合征。第二组综合征是基于第一组综合征。第二组综合征的综合征数量少于第一组综合征中的综合征数。关键方程求解器接收第二组综合征，并产生零个或多个错误位置的指示以及零个或多个误差值的指示。

29. 发明申请

US20080295044A1 METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRCUIT LAYOUT 有权
标题翻译：将设计记忆映射到集成电路布局的方法和装置
公开(公告)号：US20080295044A1
公开(公告)日：2008-11-27
申请号：US12186159
申请日：2008-08-05
申请人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/025
摘要： A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.
摘要翻译：提供了一种用于接收设计存储器列表的方法和装置，其中列表中的每种类型的设计存储器具有名称和至少一个实例。预置位模型与列表中的每个命名存储器类型相关联。列表中的设计存储器被映射到集成电路布局模式，其中至少一个存储器类型包括彼此不同地映射的第一和第二实例。映射后，第一个和第二个实例中的至少一个被重命名为具有与另一个不同的名称。然后，后置放置模型与列表中的每个命名存储器类型相关联，包括每个重命名的设计存储器的单独模型。

30. 发明授权

US07424687B2 Method and apparatus for mapping design memories to integrated circuit layout 失效
标题翻译：将设计存储器映射到集成电路布局的方法和装置
公开(公告)号：US07424687B2
公开(公告)日：2008-09-09
申请号：US11280110
申请日：2005-11-16
申请人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ilya V. Neznanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/025
摘要： A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.
摘要翻译：提供了一种用于接收设计存储器列表的方法和装置，其中列表中的每种类型的设计存储器具有名称和至少一个实例。预置位模型与列表中的每个命名存储器类型相关联。列表中的设计存储器被映射到集成电路布局模式，其中至少一个存储器类型包括彼此不同地映射的第一和第二实例。映射后，第一个和第二个实例中的至少一个被重命名为具有与另一个不同的名称。然后，后置放置模型与列表中的每个命名存储器类型相关联，包括每个重命名的设计存储器的单独模型。

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