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21. 发明专利

JP4769012B2 Nonvolatile ferroelectric memory device 有权
公开(公告)号：JP4769012B2
公开(公告)日：2011-09-07
申请号：JP2005122578
申请日：2005-04-20
申请人：株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人：熙福姜 , 進弘安 , 在眞李
IPC分类号： G11C11/22 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11502 , G11C11/22 , H01L21/84 , H01L27/11585 , H01L27/1159 , H01L29/6684 , H01L29/78391 , H01L29/7841
摘要： A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, and a floating channel layer comprising a N-type drain region, a P-type channel region and a N-type source region is formed on the insulating layer. Then, a ferroelectric layer is formed on the floating channel layer, and a word line is formed on the ferroelectric layer. As a result, the resistance state induced to the channel region is controlled depending on the polarity of the ferroelectric layer, thereby regulating the read/write operations of the memory cell array.

22. 发明专利

JP4759213B2 dram for high-speed data access 有权
公开(公告)号：JP4759213B2
公开(公告)日：2011-08-31
申请号：JP2002381359
申请日：2002-12-27
申请人：株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人：祥熏洪 , 世▲ジュン▼ 金 , 延勳鞠
IPC分类号： G11C11/401 , G06F12/00 , G06F12/06 , G06F12/08 , G11C11/4076 , G11C11/4096
CPC分类号： G06F12/0893 , G06F12/0607 , G06F2212/3042 , G11C11/4076 , G11C2207/2245

23. 发明专利

JP4758228B2 Latency control circuit of the semiconductor memory device 有权
公开(公告)号：JP4758228B2
公开(公告)日：2011-08-24
申请号：JP2005380667
申请日：2005-12-29
申请人：株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人：仁宰李
IPC分类号： G11C11/406 , G11C11/403 , G11C11/407
CPC分类号： G11C11/40615 , G11C7/12 , G11C7/22 , G11C11/406 , G11C11/4076 , G11C11/4094

24. 发明专利

JP4754191B2 Memory device including a Dll 有权
公开(公告)号：JP4754191B2
公开(公告)日：2011-08-24
申请号：JP2004194247
申请日：2004-06-30
申请人：株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人：銀庭張 , 炯東李
IPC分类号： G11C11/4076 , H03L7/081 , G06F1/10 , G11C7/22 , G11C8/00 , G11C11/407 , G11C29/02 , H03K5/13 , H03L7/06
CPC分类号： G11C11/4076 , G11C7/22 , G11C7/222 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/50012 , H03L7/0814

25. 发明专利

JP4753402B2 Method of manufacturing a FeRAM element 有权
公开(公告)号：JP4753402B2
公开(公告)日：2011-08-24
申请号：JP2000399588
申请日：2000-12-27
申请人：株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人：應烈姜
IPC分类号： H01L27/105 , H01L21/8246
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A method for manufacturing a ferroelectric random access memory (FeRAM) device, the method including the steps of forming a unit die including a transistor and a capacitor on a semiconductor substrate, testing a wafer level function for the unit die, annealing the device above Curie temperature of ferroelectric material, and carrying out a package process for the device.

26. 发明专利

JP2011160397A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011160397A
公开(公告)日：2011-08-18
申请号：JP2010089140
申请日：2010-04-08
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： KIM YONG-HOON , LEE HYUN-WOO
IPC分类号： H03K5/13 , G06F1/06 , H03K5/00
CPC分类号： H03K5/159 , H03K5/15
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having delay lines, capable of delaying an input signal with a wide variation width while maintaining the loading applied to an input terminal and the amount of operation current to minimum levels. SOLUTION: The semiconductor device includes a common delay unit 200 configured to delay an input signal in response to a delay control code ONC_PUB to output a first delayed input signal and a second delayed input signal, a first delay unit 220 configured to delay the first delayed input signal in response to a delay control code CON_1 and to output a first output signal, and a second delay unit 240 configured to delay the second delayed input signal in response to a delay control code CON_2 and to output a second output signal, and is characterized by having a predetermined length difference between a first delay route having a length for the first delayed input signal, which is transferred from the common delay unit, to pass through the first delay unit, and a second delay route having a length for the second delayed input signal, which is transferred from the common delay unit, to pass through the second delay unit. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有延迟线的半导体器件，其能够在保持施加到输入端子的负载和操作电流量至最小电平的同时延迟具有宽变化宽度的输入信号。解决方案：半导体器件包括公共延迟单元200，配置为响应于延迟控制代码ONC_PUB延迟输入信号以输出第一延迟输入信号和第二延迟输入信号，第一延迟单元220被配置为延迟响应于延迟控制代码CON_1的第一延迟输入信号并输出第一输出信号;以及第二延迟单元240，被配置为响应延迟控制代码CON_2延迟第二延迟输入信号，并输出第二输出信号并且其特征在于，具有从公共延迟单元传送的第一延迟输入信号的长度的第一延迟路径与通过第一延迟单元之间的预定长度差，以及具有长度对于从公共延迟单元传送的第二延迟输入信号，通过第二延迟单元。版权所有（C）2011，JPO＆INPIT

27. 发明专利

JP4750382B2 Method of manufacturing a flash memory device 有权
公开(公告)号：JP4750382B2
公开(公告)日：2011-08-17
申请号：JP2004192822
申请日：2004-06-30
申请人：株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人：瑛馥李
IPC分类号： H01L21/8247 , H01L27/10 , H01L21/336 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11521
摘要： The present invention relates to a method for manufacturing a flash memory device and a flash memory device manufactured by the same. In the present invention, an annealing process of a tunnel insulating film is performed at a relatively low temperature to optimize the threshold voltage of a NHVN transistor. Furthermore, in case of portions not compensated through the annealing process of the tunnel insulating film, the quality of the tunnel insulating film is compensated through a subsequent liner oxide film deposition process and a HDP oxide film annealing process. Therefore, the present invention can improve reliability of the tunnel insulating film and thus provide a flash memory device having good properties.

28. 发明专利

JP4748484B2 Gate electrode method of forming a semiconductor element 有权
公开(公告)号：JP4748484B2
公开(公告)日：2011-08-17
申请号：JP2007141320
申请日：2007-05-29
申请人：株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人：寅碩呂 , 世億張
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49
CPC分类号： H01L29/6656 , H01L21/28061 , H01L21/28247 , H01L29/6659

29. 发明专利

JP4741814B2 Gate oxide film formation method of a semiconductor element 有权
公开(公告)号：JP4741814B2
公开(公告)日：2011-08-10
申请号：JP2004191040
申请日：2004-06-29
申请人：株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人：正烈安 , 熙顕張 , ▲ミン▼ 圭李 , 占壽金
IPC分类号： H01L21/336 , H01L27/088 , H01L21/316 , H01L21/8234 , H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L21/823462 , H01L27/105 , H01L27/11534 , Y10S438/981

30. 发明专利

JP2011147165A Semiconductor device equipped with register control delay lock loop 审中-公开
标题翻译：具有寄存器控制延迟锁定环路的半导体器件
公开(公告)号：JP2011147165A
公开(公告)日：2011-07-28
申请号：JP2011052054
申请日：2011-03-09
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： KWON KI-SEOP , LEE SEONG-HOON
IPC分类号： G06F1/10 , H03K5/135 , G11C7/22 , G11C11/407 , G11C11/4076 , H03K5/00 , H03K5/13 , H03K23/40 , H03L7/00 , H03L7/08 , H03L7/081
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , H03K5/131 , H03K2005/00058 , H03K2005/00104 , H03L7/0802 , H03L7/0814
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with a register control delay lock loop (DLL) capable of reducing current consumption caused by unnecessary toggling of DLL clock. SOLUTION: The semiconductor device comprising an internal circuit that uses a DLL clock outputted from a register control DLL, includes a means for generating clock enable signals for enabling or disabling the DLL clock applied to the internal circuit, in response to an operation signal and a non-operation signal for the semiconductor device. The means for generating the clock enable signals includes: a driving means that executes pull-down or pull-up operation in response to the operation signal or non-operation signal; a reset means for resetting the output node of the driving means in response to the operation signal for the semiconductor device; and an output means which latches the signal applied to the output node of the driving means, and outputs it after buffering. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种配备有能够减少由不必要的DLL时钟切换引起的电流消耗的寄存器控制延迟锁定环（DLL）的半导体器件。解决方案：包括使用从寄存器控制DLL输出的DLL时钟的内部电路的半导体器件包括用于响应于操作产生用于使能或禁止施加到内部电路的DLL时钟的时钟使能信号的装置信号和用于半导体器件的非操作信号。用于产生时钟使能信号的装置包括：响应于操作信号或非操作信号执行下拉或上拉操作的驱动装置; 复位装置，用于响应于半导体器件的操作信号复位驱动装置的输出节点; 以及输出装置，其锁存施加到驱动装置的输出节点的信号，并在缓冲之后输出。版权所有（C）2011，JPO＆INPIT

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