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21. 发明授权

US08507348B2 Field effect transistors for a flash memory comprising a self-aligned charge storage region 有权
公开(公告)号：US08507348B2
公开(公告)日：2013-08-13
申请号：US12939282
申请日：2010-11-04
申请人： Thilo Scheiper , Sven Beyer , Uwe Griebenow , Jan Hoentschel
发明人： Thilo Scheiper , Sven Beyer , Uwe Griebenow , Jan Hoentschel
IPC分类号： H01L21/336
CPC分类号： H01L29/788 , G11C16/0425 , H01L21/28282 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.

22. 发明授权

US08497583B2 Stress reduction in chip packaging by a stress compensation region formed around the chip 有权
标题翻译：通过在芯片周围形成的应力补偿区域来减小芯片封装的应力
公开(公告)号：US08497583B2
公开(公告)日：2013-07-30
申请号：US12964448
申请日：2010-12-09
申请人： Dmytro Chumakov , Michael Grillberger , Heike Berthold , Katrin Reiche
发明人： Dmytro Chumakov , Michael Grillberger , Heike Berthold , Katrin Reiche
IPC分类号： H01L29/40
CPC分类号： H01L23/562 , H01L2224/16225 , H01L2924/01327 , H01L2924/10253 , H01L2924/19105 , H01L2924/3511 , H01L2924/00
摘要： A stress compensation region that may be appropriately positioned on a package substrate may compensate for or at least significantly reduce the thermally induced mechanical stress in a sensitive metallization system of a semiconductor die, in particular during the critical reflow process. For example, a stressor ring may be formed so as to laterally surround the chip receiving portion of the package substrate, wherein the stressor ring may efficiently compensate for the thermally induced deformation in the chip receiving portion.
摘要翻译：可以适当地定位在封装衬底上的应力补偿区域可以补偿或至少显着地降低半导体管芯的敏感金属化系统中的热致机械应力，特别是在临界回流工艺期间。例如，应力环可以形成为横向围绕封装衬底的芯片接收部分，其中应力环可以有效地补偿芯片接收部分中的热诱导变形。

23. 发明授权

US08492279B2 Method of controlling critical dimensions of vias in a metallization system of a semiconductor device during silicon-ARC etch 有权
标题翻译：在硅ARC蚀刻期间控制半导体器件的金属化系统中的通孔的临界尺寸的方法
公开(公告)号：US08492279B2
公开(公告)日：2013-07-23
申请号：US13164899
申请日：2011-06-21
申请人： Mohammed Radwan , Johann Steinmetz
发明人： Mohammed Radwan , Johann Steinmetz
IPC分类号： H01L21/311 , H01L21/302 , H01L21/00
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/31116 , H01L22/12 , H01L22/20
摘要： When forming via openings in sophisticated semiconductor devices, a silicon-containing anti-reflective coating (ARC) layer may be efficiently used for adjusting the critical dimension of the via openings by using a two-step etch process in which, in at least one of the process steps, the flow rate of a reactive gas component may be controlled to increase or reduce the resulting width of an opening in the silicon ARC layer. In this manner, the spread of critical dimensions of vias around the target value may be significantly reduced while also reducing any maintenance and rework efforts.
摘要翻译：当在复杂的半导体器件中形成通孔时，可以通过使用两步蚀刻工艺来有效地使用含硅抗反射涂层（ARC）层来调节通路孔的临界尺寸，其中在至少一个可以控制反应气体组分的流速以增加或减小硅ARC层中的开口的所得宽度。以这种方式，可以大大减少过孔的关键尺寸在目标值附近的扩散，同时也减少了任何维护和返工工作。

24. 发明授权

US08486786B2 Enhancing uniformity of a channel semiconductor alloy by forming STI structures after the growth process 有权
标题翻译：通过在生长过程之后形成STI结构来提高沟道半导体合金的均匀性
公开(公告)号：US08486786B2
公开(公告)日：2013-07-16
申请号：US12776512
申请日：2010-05-10
申请人： Stephan Kronholz , Martin Trentzsch , Richard Carter
发明人： Stephan Kronholz , Martin Trentzsch , Richard Carter
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84
摘要： When forming sophisticated gate electrode structures of transistor elements of different type, the threshold adjusting channel semiconductor alloy may be provided prior to forming isolation structures, thereby achieving superior uniformity of the threshold adjusting material. Consequently, threshold variability on a local and global scale of P-channel transistors may be significantly reduced.
摘要翻译：当形成不同类型的晶体管元件的复杂栅极结构时，可以在形成隔离结构之前提供阈值调节沟道半导体合金，从而实现阈值调节材料的优异的均匀性。因此，可以显着减少P沟道晶体管的局部和全局尺度上的阈值变化。

25. 发明授权

US08481410B1 Methods of epitaxial FinFET 有权
标题翻译：外延FinFET的方法
公开(公告)号：US08481410B1
公开(公告)日：2013-07-09
申请号：US13362398
申请日：2012-01-31
申请人： Nicholas LiCausi , Jeremy Wahl
发明人： Nicholas LiCausi , Jeremy Wahl
IPC分类号： H01L21/20
CPC分类号： H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211
摘要： Disclosed herein are various methods for better height control of the finFET patterned fins. In one example, this invention begins by depositing or growing an oxide material, for example, silicon dioxide. This oxide material is then patterned and etched to open windows or trenches to the substrate where fins will be grown. If a common channel material is desired, it is epitaxially grown in the windows. Then, some windows are covered and one pole of fins (for example nFET) are epitaxially grown in the exposed windows. The previously masked windows are opened and the newly formed fins are masked. The alternate channel material is then grown. The masked fins are then un-masked and the oxide is recessed to allow the fins to protrude from the oxide. This invention also allows for different channel materials for NMOS and PMOS.
摘要翻译：这里公开了用于更好地控制finFET图案的翅片的各种方法。在一个实例中，本发明通过沉积或生长氧化物材料，例如二氧化硅开始。然后对该氧化物材料进行图案化和蚀刻以将窗口或沟槽打开到衬底，其中翅片将被生长。如果需要共同的通道材料，则在窗户中外延生长。然后，覆盖一些窗口，并且在暴露的窗口中外延生长鳍的一个极（例如nFET）。先前掩蔽的窗户被打开，并且新形成的翅片被掩蔽。然后生长替代通道材料。掩蔽的翅片然后被掩蔽，并且氧化物凹陷以允许翅片从氧化物突出。本发明还允许用于NMOS和PMOS的不同通道材料。

26. 发明授权

US08481381B2 Superior integrity of high-k metal gate stacks by preserving a resist material above end caps of gate electrode structures 有权
标题翻译：通过在栅极电极结构的端盖上方保留抗蚀材料，可以实现高k金属栅极叠层的完整性
公开(公告)号：US08481381B2
公开(公告)日：2013-07-09
申请号：US13232711
申请日：2011-09-14
申请人： Stephan-Detlef Kronholz , Peter Javorka , Maciej Wiatr
发明人： Stephan-Detlef Kronholz , Peter Javorka , Maciej Wiatr
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L22/10 , H01L21/823807 , H01L21/823842 , H01L21/823871 , H01L21/823878 , H01L29/7848 , Y02P80/30
摘要： When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.
摘要翻译：在基于晶体管的基础上在半导体器件中形成高k金属栅极电极结构时，可以避免在N沟道晶体管的栅电极结构的端部处敏感材料的过度曝光，例如，在在将应变诱导半导体材料并入P沟道晶体管的有源区域中，从而有助于提高预定晶体管特性和性能的产量。

27. 发明授权

US08481374B2 Semiconductor element comprising a low variation substrate diode 有权
标题翻译：半导体元件包括低变化衬底二极管
公开(公告)号：US08481374B2
公开(公告)日：2013-07-09
申请号：US12914123
申请日：2010-10-28
申请人： Thilo Scheiper
发明人： Thilo Scheiper
IPC分类号： H01L21/70 , H01L21/00
CPC分类号： H01L21/84 , H01L27/0629 , H01L27/1207
摘要： A substrate diode of an SOI device may be formed on the basis of contact regions in an early manufacturing stage, i.e., prior to patterning gate electrode structures of transistors, thereby imparting superior stability to the sensitive diode regions, such as the PN junction. In some illustrative embodiments, only one additional deposition step may be required compared to conventional strategies, thereby providing a very efficient overall process flow.
摘要翻译： SOI器件的衬底二极管可以在早期制造阶段，即在图案化晶体管的栅极电极结构之前，基于接触区域形成，由此赋予敏感二极管区域（例如PN结）更好的稳定性。在一些说明性实施例中，与常规策略相比，仅需要一个额外的沉积步骤，从而提供非常有效的整体工艺流程。

28. 发明授权

US08478942B2 Method and apparatus for reducing processor cache pollution caused by aggressive prefetching 有权
标题翻译：减少由侵蚀性预取引起的处理器缓存污染的方法和装置
公开(公告)号：US08478942B2
公开(公告)日：2013-07-02
申请号：US12891027
申请日：2010-09-27
申请人： Patrick Conway
发明人： Patrick Conway
IPC分类号： G06F12/00
CPC分类号： G06F12/128 , G06F12/0862 , G06F12/0888 , G06F12/0897 , G06F2212/1021
摘要： A method and apparatus for controlling a first and second cache is provided. A cache entry is received in the first cache, and the entry is identified as having an untouched status. Thereafter, the status of the cache entry is updated to accessed in response to receiving a request for at least a portion of the cache entry, and the cache entry is subsequently cast out according to a preselected cache line replacement algorithm. The cast out cache entry is stored in the second cache according to the status of the cast out cache entry.
摘要翻译：提供了一种用于控制第一和第二高速缓存的方法和装置。在第一高速缓存中接收高速缓存条目，并且该条目被识别为具有未触动状态。此后，响应于接收到对高速缓存条目的至少一部分的请求，更新缓存条目的状态以被访问，并且高速缓存条目随后根据预先选择的高速缓存行替换算法被丢弃。根据丢弃缓存条目的状态，将丢弃的高速缓存条目存储在第二个缓存中。

29. 发明授权

US08476131B2 Methods of forming a semiconductor device with recessed source/design regions, and a semiconductor device comprising same 有权
标题翻译：形成具有凹陷源/设计区域的半导体器件的方法以及包括其的半导体器件
公开(公告)号：US08476131B2
公开(公告)日：2013-07-02
申请号：US13216791
申请日：2011-08-24
申请人： Stefan Flachowsky , Ralf Illgen , Thilo Scheiper , Ricardo P. Mikalo
发明人： Stefan Flachowsky , Ralf Illgen , Thilo Scheiper , Ricardo P. Mikalo
IPC分类号： H01L21/8238 , H01L21/331
CPC分类号： H01L21/823807 , H01L21/823814
摘要： In one example, a method disclosed herein includes forming a gate electrode structure for a PMOS transistor and a gate electrode structure for a NMOS transistor, forming a plurality of cavities in the substrate proximate the gate electrode structure of the PMOS transistor and performing an epitaxial deposition process to form raised silicon-germanium regions is the cavities. The method concludes with the step of performing a common etching process on the PMOS transistor and the NMOS transistor to define recessed regions in the substrate proximate the gate electrode structure of the NMOS transistor and to reduce the amount of the silicon-germanium material positioned above the surface of the substrate for the PMOS transistor.
摘要翻译：在一个示例中，本文公开的方法包括形成用于PMOS晶体管的栅电极结构和用于NMOS晶体管的栅电极结构，在靠近PMOS晶体管的栅电极结构的基板中形成多个空腔，并执行外延沉积形成凸起的硅 - 锗区域的过程是空腔。该方法的结论是在PMOS晶体管和NMOS晶体管上执行公共蚀刻工艺以在NMOS晶体管的栅极电极结构附近限定衬底中的凹陷区域，并且减少位于该晶体管上方的硅 - 锗材料的量用于PMOS晶体管的衬底的表面。

30. 发明授权

US08456224B2 Compensation of operating time-related degradation of operating speed by a constant total die power mode 有权
标题翻译：通过恒定的总模功率模式补偿运行时间相关的运行速度退化
公开(公告)号：US08456224B2
公开(公告)日：2013-06-04
申请号：US12577985
申请日：2009-10-13
申请人： Maciej Wiatr , Richard Heller , Rolf Geilenkeuser
发明人： Maciej Wiatr , Richard Heller , Rolf Geilenkeuser
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G06F1/26
摘要： By maintaining a substantially constant total die power during the entire lifetime of sophisticated integrated circuits, the performance degradation may be reduced. Consequently, greatly reduced guard bands for parts classification may be used compared to conventional strategies in which significant performance degradation may occur when the integrated circuits are operated on the basis of a constant supply voltage.
摘要翻译：通过在复杂集成电路的整个寿命期间保持基本上恒定的总管芯功率，可以降低性能下降。因此，与常规策略相比，可以大大减少用于部件分类的保护带，其中当基于恒定的电源电压来操作集成电路时可能发生显着的性能劣化。

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