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21. 发明授权

US5464712A Method for fabricating a phase shifting mask 失效
标题翻译：制造相移掩模的方法
公开(公告)号：US5464712A
公开(公告)日：1995-11-07
申请号：US233069
申请日：1994-04-26
申请人： O. Suk Han
发明人： O. Suk Han
IPC分类号： G03F1/30 , G03F1/68 , H01L21/027 , G03F9/00
CPC分类号： G03F1/30
摘要： A method for fabricating a phase shifting mask suitable for positive photoresist process. The method includes the steps of: (a) forming a plurality of opaque layer patterns (44) in an array at a fixed interval from each other in their width direction on a substrate (41); (b) coating an interlayer (45) on and covering the opaque layer patterns; (c) forming interlayer patterns (45) on the substrate at both longitudinal sides of each opaque layer pattern by etching the interlayer; (d) forming a plurality of insulation films (46) on the substrate between adjacent pairs of the opaque layer patterns on which the interlayer patterns are formed; (e) removing the remaining interlayer under each of the insulation films; and (f) forming a phase shifter (47) having a ninety degree area (47-2) in a region where the interlayer has been removed and a one hundred and eighty degree area (47-1) in the remainder of the region by heating the insulation film.
摘要翻译：一种用于制造适于正性光致抗蚀剂工艺的相移掩模的方法。该方法包括以下步骤：（a）在衬底（41）上以固定的间隔在其宽度方向上以阵列形式形成多个不透明层图案（44）; （b）在中间层（45）上涂覆并覆盖不透明层图案; （c）通过蚀刻中间层在每个不透明层图案的两个纵向侧在基底上形成层间图案（45）; （d）在其上形成有层间图案的不透明层图案的相邻对之间在基板上形成多个绝缘膜（46）; （e）除去每个绝缘膜下的剩余中间层; 以及（f）在去除了中间层的区域中形成有90度区域（47-2）的移相器（47），并且在该区域的其余部分中形成了一个区域（47-1）加热绝缘膜。

22. 发明授权

US5461593A Word-line driver for a semiconductor memory device 失效
标题翻译：用于半导体存储器件的字线驱动器
公开(公告)号：US5461593A
公开(公告)日：1995-10-24
申请号：US326424
申请日：1994-10-20
申请人： Seung-Bong Kim
发明人： Seung-Bong Kim
IPC分类号： G11C11/407 , G11C8/08 , G11C11/418 , G11C16/06 , G11C17/00 , G11C11/40
CPC分类号： G11C8/08
摘要： A word-line driver of a semiconductor memory device having an address buffer for receiving a row address and a word-line decoder for converting an output signal of the address buffer into a word-line decoding signal is disclosed. The word-line driver includes: a first pull-up transistor for transferring a first row selecting signal to a first node connected to a first word line, responding to the word-line decoding signal; a first pull-down transistor connected between the first node and a ground voltage terminal for pulling down a voltage level of the first node, responding to a complementary signal of the first row selecting signal; a second pull-up transistor for transferring a second row selecting signal to a second node connected to a second word line, responding to the word-line decoding signal; a second pull-down transistor connected between the second node and a ground voltage terminal for pulling down a voltage level of the second node, responding to a complementary signal of the second row selecting signal; and a switching transistor connected between the first and second nodes which is controlled by the word-line decoding signal.
摘要翻译：公开了具有用于接收行地址的地址缓冲器和用于将地址缓冲器的输出信号转换为字线解码信号的字线解码器的半导体存储器件的字线驱动器。字线驱动器包括：第一上拉晶体管，用于响应于字线解码信号，将第一行选择信号传送到连接到第一字线的第一节点; 连接在所述第一节点和地电压端子之间的第一下拉晶体管，用于根据所述第一行选择信号的互补信号来降低所述第一节点的电压电平; 第二上拉晶体管，用于响应于所述字线解码信号，将第二行选择信号传送到连接到第二字线的第二节点; 连接在所述第二节点和地电压端子之间的第二下拉晶体管，用于下降所述第二节点的电压电平;响应所述第二行选择信号的互补信号; 以及连接在第一和第二节点之间的开关晶体管，其由字线解码信号控制。

23. 发明授权

US5454705A Semiconductor mold having cavity blocks with cavities on top and bottom surfaces 失效
标题翻译：半导体模具具有在顶表面和底表面上具有空腔的空腔模块
公开(公告)号：US5454705A
公开(公告)日：1995-10-03
申请号：US993424
申请日：1992-12-21
申请人： Seung Dae Back
发明人： Seung Dae Back
IPC分类号： H01L21/56 , B29C45/02 , B29C45/14 , B29C45/26 , B29C45/10
CPC分类号： B29C45/2673
摘要： A metallic mold for molding semiconductor package including a pair of cavity blocks capable of molding two types of semi conductor packages in order to reduce manufacturing cost. The metallic mold includes an upper cavity block to be inserted in its normal state and its turned over state in an upper chase block mounted on a lower surface of a top mold base of an upper mold die which is formed at its upper surface with one type of cavities and at its lower surface with another type of cavities, and a lower cavity block to be inserted in its normal state and its turned over state in a lower chase bock mounted on a bottom mold base of a lower mold base which is formed at its upper surface with cavities mating with the another type of cavities of the upper cavity block and at its lower surface with cavities mating with the one type of cavities of the upper cavity block.
摘要翻译：一种用于模制半导体封装的金属模具，其包括能够模制两种类型的半导体封装的一对空腔模块，以便降低制造成本。该金属模具包括上模块，该上模块在上模具的上表面安装有上模具底座的下表面，其上表面具有一个类型并且在其下表面具有另一种类型的空腔，以及下腔体块，其在正常状态下被插入，并且在下模具底座中的翻盖状态安装在下模具底座上，下模具底座形成在下模具底座上，其上表面具有与上腔模块的另一种类型的空腔配合的空腔，并且在其下表面具有与上腔模块的一种类型的空腔配合的空腔。

24. 发明授权

US5436577A CMOS tri-state buffer circuit and operation method thereof 失效
标题翻译： CMOS三态缓冲电路及其操作方法
公开(公告)号：US5436577A
公开(公告)日：1995-07-25
申请号：US97256
申请日：1993-07-23
申请人： Cheol-Hee Lee
发明人： Cheol-Hee Lee
IPC分类号： H03K19/0175 , H03K17/16 , H03K19/017 , H03K19/00
CPC分类号： H03K17/163
摘要： A 3-state buffer circuit applicable for a CMOS output drive circuit is disclosed. The output circuit provides reduced ground noise and delay time of an output signal by decreasing a counter-electromotive force generated upon turning ON of the output transistor. The circuit includes a subsidiary drive circuit for applying a voltage less than the power source Vcc to a gate of an NMOS transistor connected on the ground side of the drive circuit so that generation of the counter-electromotive force is minimized.
摘要翻译：公开了一种适用于CMOS输出驱动电路的3态缓冲电路。输出电路通过减小在输出晶体管导通时产生的反电动势来减小输出信号的接地噪声和延迟时间。电路包括用于将小于电源Vcc的电压施加到连接在驱动电路的接地侧上的NMOS晶体管的栅极的辅助驱动电路，从而使反电动势的产生最小化。

25. 发明授权

US5426318A Horizontal charge coupled device having a multiple reset gate 失效
标题翻译：具有复位门的水平电荷耦合器件
公开(公告)号：US5426318A
公开(公告)日：1995-06-20
申请号：US867243
申请日：1992-04-10
申请人： Seo K. Lee
发明人： Seo K. Lee
IPC分类号： H01L27/148 , H01L21/339 , H01L29/423 , H01L29/762 , H01L29/768 , H04N5/335 , H04N5/357 , H04N5/369 , H04N5/372 , H01L29/78
CPC分类号： H01L29/42396 , H01L29/76816
摘要： A horizontal charge coupled device (HCCD) is provided with a multiple reset gate in order to establish a more stable, less noisy voltage in an output node floating diffusion. Charges are transferred from an input of the HCCD to the floating diffusion by multiple, overlapping gate structures. Signal charges are detected or read out from the floating diffusion through an amplifier/inverter circuit. Periodically, the voltage of the floating diffusion is established to a reference level by application of a reset signal to a multiple reset gate structure, which results in charges in the floating diffusion being transferred to a reset drain. Noise induced by the reset operation is lessened on average due to the multiple reset gate structure.
摘要翻译：水平电荷耦合器件（HCCD）具有多个复位栅极，以便在输出节点浮动扩散中建立更稳定，更低噪声的电压。充电通过多个重叠的栅极结构从HCCD的输入传输到浮动扩散。通过放大器/逆变器电路从浮动扩散中检测或读出信号电荷。周期性地，浮置扩散的电压通过将复位信号施加到多重复位栅极结构而建立到参考电平，这导致浮动扩散中的电荷被传送到复位漏极。由于多重复位门结构，复位操作引起的噪声平均减小。

26. 发明授权

US5418790A Interference grasping test mode circuit for a semiconductor memory device 失效
标题翻译：半导体存储器件的干涉测试模式电路
公开(公告)号：US5418790A
公开(公告)日：1995-05-23
申请号：US995974
申请日：1992-12-23
申请人： Jong H. Kim
发明人： Jong H. Kim
IPC分类号： G01R31/28 , G11C29/26 , G11C29/34 , G11C29/36 , G11C29/48 , H01L21/66 , G11C29/00
CPC分类号： G11C29/36 , G11C29/26 , G11C29/48
摘要： A test mode circuit for a memory device for, in a test mode, transforming information to be stored in the memory device and information being read from the memory device and selecting simultaneously information stored in cell arrays in the memory device, so as to grasp interferences between adjacent cells and between adjacent data bus lines. The circuit comprises a cell array section having a plurality of cell arrays for storing input data therein, a first switching section for selecting one of test and normal modes and selecting one of the plurality of cell arrays in the normal mode, a first logic section for transferring desired information simultaneously to the cell array section in response to a clock signal in the test mode, a second logic section responsive to the clock signal for outputting directly output data signals from the plurality of cell arrays or inverting the data signals and outputting the inverted data signals, a third logic section for, in the test mode, inputting output signals from the second logic section and discriminating whether the data signals from the plurality of cell arrays are the same, and a second switching section for selecting, as its output signal, an output, signal from the third logic section in the test mode and the data signal from the selected one of cell arrays in the normal mode.
摘要翻译：一种用于存储器件的测试模式电路，用于在测试模式中将要存储在存储器件中的信息和从存储器件读取的信息进行变换，并同时选择存储在存储器件中的单元阵列中的信息，从而掌握干扰在相邻小区之间和相邻数据总线之间。该电路包括具有用于存储输入数据的多个单元阵列的单元阵列部分，用于选择测试和正常模式中的一个并在正常模式中选择多个单元阵列中的一个的第一切换部分，第一逻辑部分响应于测试模式中的时钟信号，将期望的信息同时传送到单元阵列部分;响应于时钟信号的第二逻辑部分，用于从多个单元阵列直接输出输出数据信号或反相数据信号并输出反相数据信号，第三逻辑部分，用于在测试模式中输入来自第二逻辑部分的输出信号，并且辨别来自多个单元阵列的数据信号是否相同;以及第二切换部分，用于选择其输出信号，来自测试模式中第三逻辑部分的输出信号和来自正常模式下的所选单元阵列的数据信号。

27. 发明授权

US5406105A Electro static discharge protecting circuit 失效
标题翻译：静电放电保护电路
公开(公告)号：US5406105A
公开(公告)日：1995-04-11
申请号：US260196
申请日：1994-06-15
申请人： Kyung S. Lee
发明人： Kyung S. Lee
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L29/06 , H02H3/20
CPC分类号： H01L27/0251
摘要： An electro static discharge protection circuit capable of achieving an improvement in ESD protection characteristic by an isolation between the inner cell ground and the ESD protection circuit ground and use of a field oxide transistor. The protection circuit includes first and third p type wells formed at a peripheral circuit region of a n type substrate and a second p type well formed at a cell region of the substrate, a first p.sup.+ type impurity-diffused region, first, second and third n.sup.+ type impurity-diffused regions, all of the impurity-diffused regions being formed in the first p type well, a second p.sup.+ type impurity-diffused region formed in the second p type well, a third p.sup.+ type impurity-diffused region, fourth, fifth and sixth n.sup.+ type impurity-diffused regions, all of the impurity-diffused regions being formed in the third p type well, a field oxide film formed over a surface portion of the n type substrate between adjacent high concentration impurity-diffused regions formed in each of the first and third p type wells, and gate electrodes respectively formed on portions of the field oxide film disposed between the second and third n type impurity-diffused regions and between the fourth and fifth n type impurity-diffused regions.
摘要翻译：一种静电放电保护电路，其能够通过内部单元接地和ESD保护电路接地之间的隔离以及场氧化物晶体管的使用来实现ESD保护特性的改善。保护电路包括在基板的外围电路区域形成的第一和第三p型阱，以及在基板的单元区域形成的第二p型阱，第一p +型杂质扩散区，第一，第二和第三n + 在第一p型阱中形成所有杂质扩散区，在第二p型阱中形成的第二p +型杂质扩散区，第三p +型杂质扩散区，第四，第五和第六n +型杂质扩散区域，在第三p型阱中形成所有杂质扩散区域，形成在每个形成的相邻高浓度杂质扩散区域之间的n型衬底的表面部分上的场氧化物膜的第一和第三p型阱以及分别形成在设置在第二和第三n型杂质扩散区之间以及第四和第五n型杂质之间的场氧化物膜的部分上的栅电极扩散区域。

28. 发明授权

US5393373A Methods of patterning and manufacturing semiconductor devices 失效
标题翻译：图案化和制造半导体器件的方法
公开(公告)号：US5393373A
公开(公告)日：1995-02-28
申请号：US135197
申请日：1993-10-12
申请人： Young K. Jun , Sa K. Ra , Dong W. Kim , Hyun H. Seo , Sung C. Kim , Jun K. Kim
发明人： Young K. Jun , Sa K. Ra , Dong W. Kim , Hyun H. Seo , Sung C. Kim , Jun K. Kim
IPC分类号： H01L21/02 , H01L21/033 , H01L21/8242 , H01L27/108 , H01L21/306 , B44C1/22
CPC分类号： H01L27/10817 , H01L21/0337 , H01L27/10852 , H01L28/92 , Y10S438/942
摘要： Methods of hyperfine patterning and manufacturing semiconductor devices. Steps in accordance with the present invention include coating a hemisphere particle layer having hills and valleys on a layer to be etched, the hemisphere particle layer having an etch selectivity higher than that of the first layer, filling the valleys of the hemisphere particle layer with a second layer having an etch selectivity higher than that of the hemisphere particle layer, and etching back the hills of the hemisphere particle layer to expose the first layer by using the second layer as a mask, and etching the first layer. By virtue of the hemisphere particle layer having alternating hills and valleys, it is possible to accomplish a hyperfine patterning of about 0.1 .mu.m. Since the mean size and the density of hills and valleys of the hemisphere layer can be controlled, the pattern size also can be controlled. Where the present invention is applied to capacitors of semiconductor memory elements, the capacitor node surface area can be increased, depending on the etched back depth of a polysilicon layer.
摘要翻译：超精细图案化和制造半导体器件的方法。根据本发明的步骤包括在待蚀刻的层上涂覆具有山丘和谷的半球粒子层，该半球粒子层的蚀刻选择性高于第一层的蚀刻选择性，将半球粒子层的谷部填充到半球粒子层的谷部第二层具有比半球颗粒层的蚀刻选择性更高的蚀刻选择性，并且通过使用第二层作为掩模蚀刻半球粒子层的山丘以暴露第一层，并蚀刻第一层。由于半球颗粒层具有交替的山丘和山谷，可以实现约0.1μm的超精细图案化。由于可以控制半球层的平均尺寸和丘陵和山谷的密度，因此也可以控制图案尺寸。在将本发明应用于半导体存储器元件的电容器的情况下，可以根据多晶硅层的蚀刻回深度来增加电容器节点表面积。

29. 发明授权

US5389557A Process for formation of LDD transistor, and structure thereof 失效
标题翻译： LDD晶体管的形成方法及其结构
公开(公告)号：US5389557A
公开(公告)日：1995-02-14
申请号：US75633
申请日：1993-06-10
申请人： Goo Jung-Suk
发明人： Goo Jung-Suk
IPC分类号： H01L21/336 , H01L29/08 , H01L29/10 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66492 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/41783 , H01L29/6659 , H01L29/78 , H01L29/66545
摘要： A process for formation of an LDD transistor and a structure thereof are disclosed in which the junction capacitance and the body effect can be properly reduced. In the conventional LDD transistors, the punch-through problem is serious, and the improved conventional LDD transistor also, there is a limit in increasing the channel concentration, as well as the body effect being increased. The present invention gives solutions to the above problems by arranging that the junction thicknesses of n+ source and drain become smaller than the junction thicknesses of n- regions, and that a p type pocket 6 be formed only near a gate and a p type pocket 6.
摘要翻译：公开了一种用于形成LDD晶体管的方法及其结构，其中可以适当地减少结电容和体效应。在传统的LDD晶体管中，穿通问题是严重的，并且改进的常规LDD晶体管也增加了沟道浓度以及增加体效应的限制。本发明通过设置n +源极和漏极的结厚变得小于n-区的结的厚度，并且仅在栅极附近形成p型槽6和p型槽6来解决上述问题。

30. 发明授权

US5366909A Method for fabricating thin film transistor 失效
标题翻译：制造薄膜晶体管的方法
公开(公告)号：US5366909A
公开(公告)日：1994-11-22
申请号：US200770
申请日：1994-02-23
申请人： Seung R. Song , Hong S. Kim
发明人： Seung R. Song , Hong S. Kim
IPC分类号： G11B15/32 , H01L21/335 , H01L21/336 , H01L21/8244 , H01L29/78 , H01L29/786 , H01L21/265
CPC分类号： H01L29/66757 , H01L27/11 , H01L29/78624 , Y10S148/15
摘要： A method for fabricating a thin film transistor capable of increasing an ON/OFF current ratio and decreasing a consumption of electric power. The method includes the steps of sequentially depositing an insulating film and a first, high concentration p type semiconductor layer over a substrate, selectively removing a portion of the first semiconductor layer corresponding to a channel region, thereby forming a source region and a drain region, depositing a second, undoped semiconductor layer over the entire exposed surface of the resulting structure and implanting ions for controlling a threshold voltage in the second semiconductor layer, sequentially depositing a gate insulating film and a third semiconductor layer for a gate electrode over the entire exposed surface of the resulting structure and patterning the third semiconductor layer and the gate insulating film such that the third semiconductor layer and the gate insulating film are overlapped with the source region while being offset to the drain region, thereby forming the gate electrode, implanting p type impurity ions in a low concentration in an exposed portion of the second semiconductor layer using the gate electrode as a mask, and diffusing the p type impurity ions doped in both the source region and the drain region into the second semiconductor layer.
摘要翻译：一种制造能够增加ON / OFF电流比并降低电力消耗的薄膜晶体管的方法。该方法包括以下步骤：在衬底上依次沉积绝缘膜和第一高浓度p型半导体层，选择性地去除对应于沟道区的第一半导体层的一部分，从而形成源区和漏区，在所得结构的整个暴露表面上沉积第二未掺杂的半导体层，并且注入用于控制第二半导体层中的阈值电压的离子，在整个暴露表面上依次沉积栅极绝缘膜和用于栅电极的第三半导体层的结构，并且使第三半导体层和栅极绝缘膜图案化，使得第三半导体层和栅极绝缘膜在偏移到漏极区域的同时与源极区域重叠，从而形成栅电极，注入p型杂质在t的暴露部分中低浓度的离子使用栅极电极作为掩模的第二半导体层，以及将掺杂在源极区域和漏极区域中的p型杂质离子扩散到第二半导体层中。

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