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201. 发明授权

US5705417A Method for forming self-aligned silicide structure 失效
标题翻译：形成自对准硅化物结构的方法
公开(公告)号：US5705417A
公开(公告)日：1998-01-06
申请号：US665664
申请日：1996-06-19
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/66545 , Y10S148/147
摘要： An improved method for forming a self-aligned silicide structure with reduced bridging effect is disclosed. The method includes forming a gate oxide on a substrate. Then a polysilicon layer is formed on the gate oxide. The polysilicon layer and the gate oxide are then patterned using a photoresist mask which defines a gate region. Next, the substrate is lightly-doped to form lightly-doped source/drain regions. Dielectric spacers are formed on a sidewall of the gate, and portions of the polysilicon layer and the substrate are removed with the dielectric spacers serving as a mask. A conductive layer is formed on the gate and the substrate, and is then silicided. Afterward, the unsilicided portions of the conductive layer are removed. Finally, heavily-doped source/drain regions are formed on the substrate with the dielectric spacers serving as a heavy-doping mask.
摘要翻译：公开了一种用于形成具有降低桥接效应的自对准硅化物结构的改进方法。该方法包括在衬底上形成栅极氧化物。然后在栅极氧化物上形成多晶硅层。然后使用限定栅极区域的光致抗蚀剂掩模对多晶硅层和栅极氧化物进行构图。接下来，衬底被轻掺杂以形成轻掺杂的源/漏区。电介质间隔物形成在栅极的侧壁上，并且多孔层和衬底的部分被用作掩模的电介质间隔物去除。在栅极和衬底上形成导电层，然后被硅化。之后，去除导电层的未硅化部分。最后，在衬底上形成重掺杂的源极/漏极区，其中介电间隔物用作重掺杂掩模。

202. 发明授权

US5677228A Method of fabricating a resistor in an integrated circuit 失效
标题翻译：在集成电路中制造电阻器的方法
公开(公告)号：US5677228A
公开(公告)日：1997-10-14
申请号：US788679
申请日：1997-01-24
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/02 , H01L21/70 , H01L27/00
CPC分类号： H01L28/20 , Y10S148/036
摘要： A method for forming a resistor in an integrated circuit is disclosed. The method includes forming a composite mask layer on a substrate, and forming a photoresist layer on the composite mask layer to define a trench area. Portions of the composite mask layer and the substrate are then removed using the photoresist layer as an etching mask, thereby forming a trench in the substrate. An isolation oxide layer is conformally formed on the composite mask layer, the sidewalls of the trench, and a bottom of the trench. Further, an undoped polysilicon layer is conformally formed on the isolation oxide layer. Thereafter, a doped polysilicon layer is formed over the undoped polysilicon layer, thereby filling the trench. The doped polysilicon layer is etched back using a first etchant, using the undoped polysilicon layer as an etch stop. The doped polysilicon layer and the undoped polysilicon layer are further etched back using a second etchant different from the first etchant, thereby forming a flat plug, where the second etchant has the same etch rate to both the undoped polysilicon layer and the doped polysilicon layer. Finally, the undoped polysilicon and the doped polysilicon layer are annealed to diffuse dopants of the doped polysilicon layer into the undoped polysilicon layer.
摘要翻译：公开了一种在集成电路中形成电阻器的方法。该方法包括在衬底上形成复合掩模层，并在复合掩模层上形成光致抗蚀剂层以限定沟槽区域。然后使用光致抗蚀剂层作为蚀刻掩模去除复合掩模层和基板的一部分，从而在基板中形成沟槽。在复合掩模层，沟槽的侧壁和沟槽的底部上共形地形成隔离氧化物层。此外，在隔离氧化物层上保形地形成未掺杂的多晶硅层。此后，在未掺杂多晶硅层上形成掺杂多晶硅层，由此填充沟槽。使用第一蚀刻剂将掺杂的多晶硅层回蚀刻，使用未掺杂的多晶硅层作为蚀刻停止层。使用不同于第一蚀刻剂的第二蚀刻剂进一步回蚀掺杂多晶硅层和未掺杂多晶硅层，从而形成扁平插头，其中第二蚀刻剂对未掺杂多晶硅层和掺杂多晶硅层具有相同的蚀刻速率。最后，将未掺杂多晶硅和掺杂多晶硅层进行退火，以将掺杂多晶硅层的掺杂剂扩散到未掺杂的多晶硅层中。

203. 发明授权

US5604146A Method to fabricate a semiconductor memory device having an E-shaped storage node 失效
标题翻译：制造具有E形存储节点的半导体存储器件的方法
公开(公告)号：US5604146A
公开(公告)日：1997-02-18
申请号：US661245
申请日：1996-06-10
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method is described for forming a dynamic random access memory cell with an increased capacitance capacitor. Device structures, including a capacitor node contact region, are formed in and on the semiconductor substrate. A dielectric layer and a thick insulating layer are deposited over the device structures and planarized. A contact is opened to the capacitor node contact region. A first layer of polysilicon is deposited filling the contact opening. The portion contacting the node contact region forms the bottom electrode of the capacitor. A portion of the polysilicon layer is etched away to form a well above the contact opening. A layer of silicon oxide is deposited within the well and is etched back to leave spacers on the sidewalls of the well. A second layer of polysilicon is deposited over the first polysilicon layer and within the well. The second polysilicon layer is removed except where it forms a plug within the well. The spacers are removed leaving gaps on either side of the plug. The first polysilicon layer is patterned so that an E-shaped storage node structure having three prongs pointing upward is formed. The plug forms the central prong and the outer two prongs are formed by the patterned first polysilicon layer. A capacitor dielectric layer is deposited over all surfaces of the E-shaped structure. A third polysilicon layer is deposited over the capacitor dielectric covering and filling the gaps of the E-shaped structure and forming the top capacitor electrode.
摘要翻译：描述了一种用于形成具有增加的电容电容器的动态随机存取存储器单元的方法。包括电容器节点接触区域的器件结构形成在半导体衬底中和半导体衬底上。介电层和厚绝缘层沉积在器件结构上并进行平面化处理。一个触点打开到电容器节点接触区域。沉积第一层多晶硅填充接触开口。接触节点接触区域的部分形成电容器的底部电极。蚀刻掉多晶硅层的一部分以在接触开口上方形成孔。氧化硅层沉积在阱内并被回蚀刻以在阱的侧壁上留下间隔物。在第一多晶硅层和阱内沉积第二层多晶硅。去除第二多晶硅层，除非它在孔内形成插塞。去除间隔物，留下插头两侧的间隙。对第一多晶硅层进行图案化，形成具有向上指向的三个尖头的E形存储节点结构。插头形成中央插脚，外部两个插脚由图案化的第一多晶硅层形成。电容器电介质层沉积在E形结构的所有表面上。第三多晶硅层沉积在覆盖并填充E形结构的间隙并形成顶部电容器电极的电容器电介质上。

204. 发明授权

US5595929A Method for fabricating a dram cell with a cup shaped storage node 失效
标题翻译：用于形成具有杯形存储节点的电容器的方法
公开(公告)号：US5595929A
公开(公告)日：1997-01-21
申请号：US585615
申请日：1996-01-16
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/60
摘要： A method and resultant structure, is described for fabricating a DRAM cell having a cup-shaped capacitor connected to a MOS transistor with source and drain regions. A cylindrical bottom portion of a storage electrode is connected to and extends up from the source region of the transistor. The storage electrode has a solid cup shaped top portion over the bottom portion. The method comprises forming an interlayer insulating film over the MOS transistor and forming a photoresist layer with an opening over the source. The interlayer film is isotropically etched through the opening to form a cup shaped cavity. Next, the interlayer is anisotropically etch through the same photoresist opening to form a contact opening exposing the source. A polysilicon layer is formed filling the contact hole and the cup shaped cavity thereby forming a cup shaped storage electrode, The interlayer film is then removed. A capacitor dielectric and a top electrode are formed over the storage electrode to complete the cup shaped capacitors.
摘要翻译：描述了一种制造具有连接到具有源极和漏极区域的MOS晶体管的杯形电容器的DRAM单元的方法和结果结构。存储电极的圆柱形底部连接到晶体管的源极区域并且从晶体管的源极区域向上延伸。存储电极在底部上方具有固体杯形顶部。该方法包括在MOS晶体管上形成层间绝缘膜，并在源极上形成具有开口的光致抗蚀剂层。通过开口各向同性蚀刻中间膜以形成杯形腔。接下来，中间层通过相同的光致抗蚀剂开口进行各向异性蚀刻，以形成暴露源的接触开口。形成多晶硅层，填充接触孔和杯形空腔，从而形成杯形储存电极。然后去除层间膜。在存储电极上形成电容器电介质和顶电极以完成杯形电容器。

205. 发明授权

US5552620A Vertical transistor with high density DRAM cell and method of making 失效
标题翻译：具有高密度DRAM单元的垂直晶体管及其制造方法
公开(公告)号：US5552620A
公开(公告)日：1996-09-03
申请号：US428763
申请日：1995-04-24
申请人： Chih-Yuan Lu , Horng-Huei Tseng
发明人： Chih-Yuan Lu , Horng-Huei Tseng
IPC分类号： H01L27/108
CPC分类号： H01L27/10841 , Y10S257/90
摘要： There is shown a method for fabricating a vertical DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements and a capacitor. There is provided a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate. A pattern is formed of bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes so that it covers the gate dielectric and the field oxide isolation. A silicon nitride layer is formed over the doped polysilicon layer. Patterning and etching is done to the silicon nitride layer and doped polysilicon layer to form the opening for the capacitor node contact to the buried source/drain of the vertical field effect transistor (switching device for the storage signal) and establish said gate electrode in the hole and word line pattern over the field oxide insulator. A silicon oxide spacer is formed over the sidewalls of the silicon nitride and doped polysilicon layer. A capacitor is formed in and over the hole to complete the vertical DRAM cell.
摘要翻译：示出了制造垂直DRAM单元的方法，其包括具有栅电极和源极/漏极元件的电场效应晶体管和电容器。在硅衬底中提供了场氧化物隔离的图案，其中存在到硅衬底的开口图案。图案由位线和具有位于每个到所述硅衬底的每个开口内的孔的线的图案形成，孔和位线的线彼此垂直，并且线在所述硅衬底的计划位置处交叉垂直DRAM单元以与硅衬底的开口的图案形成。在孔的表面上形成栅极电介质。在孔内和上方形成掺杂多晶硅层，使其覆盖栅极电介质和场氧化物隔离。在掺杂多晶硅层上形成氮化硅层。对氮化硅层和掺杂多晶硅层进行图案化和蚀刻，以形成用于电容器节点接触到垂直场效应晶体管（用于存储信号的开关器件）的掩埋源极/漏极的开口，并在孔和字线图形在场氧化物绝缘体上。在氮化硅和掺杂多晶硅层的侧壁上形成氧化硅隔离物。在孔内和上方形成电容器以完成垂直DRAM单元。

206. 发明授权

US5552334A Method for fabricating a Y-shaped capacitor in a DRAM cell 失效
标题翻译：在DRAM单元中制造Y形电容器的方法
公开(公告)号：US5552334A
公开(公告)日：1996-09-03
申请号：US589281
申请日：1996-01-22
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： The present invention provides a method of manufacturing a capacitor for a DRAM which uses one mask to define both the node contact hole and the bottom electrode. This novel one mask method uses lateral etch (e.g., oxygen plasma) to enlarge a first opening (the node contact opening) in the resist layer to define a slightly larger second opening which defines the storage electrode. This method reduces the masking steps used and therefore reduces process costs and increases yields. The process comprises forming an insulation layer and a resist layer having a first opening over an active area. A node contact hole is partially etched through the insulation layer. Next, the first opening is enlarged with an lateral etch to form a second slightly larger opening. A storage electrode hole is formed in the insulation layer with the same dimensions as the second opening and the node contact hole is extended to expose the node contact. The resist layer is removed. A polysilicon layer is formed that completely fills the node contact hole and coats the sidewalls of the storage electrode hole. Masking and etching steps form a Y-shaped storage electrode from the remaining first polysilicon layer coating the storage electrode hole.
摘要翻译：本发明提供一种制造用于DRAM的电容器的方法，其使用一个掩模来限定节点接触孔和底部电极。这种新颖的一种掩模方法使用横向蚀刻（例如，氧等离子体）来扩大抗蚀剂层中的第一开口（节点接触开口），以限定限定存储电极的略大的第二开口。该方法减少了使用的掩蔽步骤，从而降低了工艺成本并提高了产量。该方法包括在有源区上形成绝缘层和抗蚀剂层，其具有第一开口。通过绝缘层部分蚀刻节点接触孔。接下来，第一开口用横向蚀刻扩大以形成第二稍大的开口。在绝缘层中形成与第二开口相同尺寸的存储电极孔，并且延伸节点接触孔以露出节点接触。去除抗蚀剂层。形成多晶硅层，其完全填充节点接触孔并涂覆存储电极孔的侧壁。掩模和蚀刻步骤从涂覆存储电极孔的剩余的第一多晶硅层形成Y形存储电极。

207. 发明授权

US5550077A DRAM cell with a comb-type capacitor 失效
标题翻译：具有梳状电容器的DRAM单元
公开(公告)号：US5550077A
公开(公告)日：1996-08-27
申请号：US435203
申请日：1995-05-05
申请人： Horng-Huei Tseng , Chih-Yuan Lu
发明人： Horng-Huei Tseng , Chih-Yuan Lu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： An efficient method for manufacturing a comb-type capacitor for use as part of a DRAM cell in a silicon integrated circuit is described. A three toothed comb is created by first forming a central pedestal of polysilicon, providing oxide spacers on the vertical sides of said pedestal, coating said spacers with an additional layer of polysilicon, and then etching away said spacers thereby creating the comb structure. In addition to the comb, the method of the present invention also leads to the formation of a projecting rim of polysilicon that runs around all four sides of the capacitor structure, thereby further increasing its effective surface beyond that due to the comb.
摘要翻译：描述了一种用于制造用作硅集成电路中的DRAM单元的一部分的梳状电容器的有效方法。通过首先形成多晶硅的中心基座，在所述基座的垂直侧上提供氧化物隔离物，用附加的多晶硅层涂覆所述间隔物，然后蚀刻所述间隔物从而形成梳状结构，从而产生三齿梳。除了梳子之外，本发明的方法还导致在电容器结构的所有四个侧面上形成突出的多晶硅边缘，从而进一步增加其有效表面超过由于梳子的有效表面。

208. 发明授权

US5534457A Method of forming a stacked capacitor with an "I" shaped storage node 失效
标题翻译：用“I”形存储节点形成堆叠电容器的方法
公开(公告)号：US5534457A
公开(公告)日：1996-07-09
申请号：US375783
申请日：1995-01-20
申请人： Horng-Huei Tseng , Chih-Yuan Lu
发明人： Horng-Huei Tseng , Chih-Yuan Lu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/60 , H01L28/86
摘要： A DRAM having a high capacitance stacked capacitor is fabricated by forming gate structures in the device areas and lines over field oxide areas on a substrate. A first insulating layer is formed and patterned to leave the source/drain structures open in the device areas where electrical contact is desired to the stacked capacitors. A bottom electrode of the capacitor is now formed by depositing and patterning a second polysilicon layer and a second insulating layer. Next the second polysilicon layer is laterally etched so that portions of the second polysilicon layer are etched out underneath from the second insulating layer. A third polysilicon layer is formed on the vertical sidewalls of the second polysilicon layer. A capacitor dielectric layer is deposited over the substrate surface and patterned so that portions remain covering the second and third polysilicon layers. A top electrode is formed over the capacitor dielectric layer.
摘要翻译：通过在衬底上的场氧化物区域上的器件区域和线中形成栅极结构来制造具有高电容层叠电容器的DRAM。第一绝缘层被形成并图案化以使得源极/漏极结构在需要电接触到堆叠的电容器的器件区域中断开。电容器的底部电极现在通过沉积和构图第二多晶硅层和第二绝缘层而形成。接下来，第二多晶硅层被横向蚀刻，使得第二多晶硅层的部分在第二绝缘层的下方被蚀刻掉。在第二多晶硅层的垂直侧壁上形成第三多晶硅层。电容器介电层沉积在衬底表面上并被图案化，使得部分保持覆盖第二和第三多晶硅层。在电容器电介质层上形成顶部电极。

209. 发明授权

US5192702A Self-aligned cylindrical stacked capacitor DRAM cell 失效
标题翻译：自对准圆柱形堆叠电容器DRAM单元
公开(公告)号：US5192702A
公开(公告)日：1993-03-09
申请号：US811991
申请日：1991-12-23
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L27/108
CPC分类号： H01L27/10817
摘要： A method for fabricating a dynamic random access memory having a high capacitance stacked capacitor begins by selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices. A gate dielectric layer is formed on the substrate in the device areas. A relatively thick first layer of polysilicon is deposited on the field oxide areas and the device areas. Portions of the first polysilicon layer is removed while leaving portions thereof for the gate structure in the device areas, and portions over the field oxide areas. A first insulator layer composed at least in part of silicon nitride is formed over the device and field oxide areas. The stacked capacitors are now formed by first depositing a second polysilicon layer over the device and field oxide areas. An etch mask is now formed on the second polysilicon layer and the second polysilicon layer is anisotropically etching to form a shell-shaped second polysilicaon layer. A capacitor dielectric layer is formed over the shell-shaped second polysilicon layer. A third polysilicon layer is deposited and patterned as the top storage node electrode to complete the stacked capacitors. The etch mask can either be formed in part by a lateral etching of a resist mask or is formed in part by use of a sidewall spacer structure and mask. The first insulator layer is patterned to expose the source/drain structures to electrical contact either before or after the deposition of the second polysilicon layer.
摘要翻译：制造具有高电容层叠电容器的动态随机存取存储器的方法是通过在半导体衬底的表面上选择性地形成相对厚的场氧化物区域，同时留出用于制造场效应器件的器件区域。在器件区域中的衬底上形成栅极电介质层。相对厚的第一多晶硅层沉积在场氧化物区域和器件区域上。去除第一多晶硅层的部分，同时留下用于器件区域中的栅极结构的部分，以及场氧化物区域上的部分。至少部分由氮化硅构成的第一绝缘体层形成在器件和场氧化物区域上。现在通过首先在器件和场氧化物区域上沉积第二多晶硅层来形成堆叠的电容器。现在在第二多晶硅层上形成蚀刻掩模，并且第二多晶硅层进行各向异性蚀刻以形成壳形第二聚硅氧烷层。在壳状第二多晶硅层上形成电容器电介质层。沉积第三多晶硅层并将其图案化为顶部存储节点电极以完成堆叠的电容器。蚀刻掩模可以部分地通过抗蚀剂掩模的横向蚀刻形成，或者部分地通过使用侧壁间隔物结构和掩模形成。图案化第一绝缘体层，以在第二多晶硅层沉积之前或之后使源极/漏极结构暴露于电接触。

210. 发明申请

US20100159693A1 Method of Forming Via Recess in Underlying Conductive Line 审中-公开
标题翻译：在导电线路中通过凹陷形成的方法
公开(公告)号：US20100159693A1
公开(公告)日：2010-06-24
申请号：US12715175
申请日：2010-03-01
申请人： Chung-Shi Liu , Chen-Hua Yu , Horng-Huei Tseng
发明人： Chung-Shi Liu , Chen-Hua Yu , Horng-Huei Tseng
IPC分类号： H01L21/768
CPC分类号： H01L23/5329 , H01L21/76802 , H01L21/76805 , H01L21/76807 , H01L21/76816 , H01L21/76834 , H01L21/76844 , H01L21/76847 , H01L23/5226 , H01L23/53214 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device includes forming a via in a dielectric layer that opens to a conductive line underlying the dielectric layer, and forming a via recess in the conductive line at the via. The via recess in the conductive line has a depth ranging from about 100 angstroms to about 600 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line. The via recess may have a same size or smaller cross-section area than that of the via, for example. Such via structure may be part of a dual damascene structure in an intermetal dielectric structure, for example.
摘要翻译：制造半导体器件的方法包括在介电层下方形成导电线的电介质层中形成通孔，以及在通孔的导电线中形成通路凹槽。导线中的通路凹槽的深度范围为约100埃至约600埃。通孔填充材料填充通孔凹部并且至少部分地填充通孔，使得通孔填充材料电连接到导电线。例如，通孔凹部可以具有与通孔相同的尺寸或更小的横截面面积。例如，这种通孔结构可以是金属间电介质结构中的双镶嵌结构的一部分。

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