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11. 实用新型

JPS58150148U 失效
公开(公告)号：JPS58150148U
公开(公告)日：1983-10-07
申请号：JP4675882
申请日：1982-03-30
IPC分类号： G05B15/02 , G05B7/02 , G05B9/02 , G05B11/36 , G06F3/05 , G06J1/00 , G06J3/00

12. 发明专利

JPS525437A OVERLOAD PREVENTION COUNTERMEASURE COMPUTING SYSTEM FOR POWER SYSTEM 失效
公开(公告)号：JPS525437A
公开(公告)日：1977-01-17
申请号：JP8224275
申请日：1975-07-02
申请人： TOKYO ELECTRIC POWER CO , MITSUBISHI ELECTRIC CORP
发明人： SAITOU OSAMU , KOIZUMI KINNOSUKE , TSUJI TOSHIHIKO
IPC分类号： H02J3/00 , G06J1/00 , G06J3/00
摘要： PURPOSE:The power system cascade trip causing the great interruption of the service preventing system to simplify the of the high speed overload preventing countermeasure with the constitution of the hybrid computing system.

13. 发明授权

US6144327A Programmably interconnected programmable devices 失效
标题翻译：可编程互连的可编程器件
公开(公告)号：US6144327A
公开(公告)日：2000-11-07
申请号：US909838
申请日：1997-08-12
申请人： Robert J Distinti , Harry F Smith
发明人： Robert J Distinti , Harry F Smith
IPC分类号： G06F15/78 , G06J3/00 , H03M1/00
CPC分类号： G06F15/7867 , G06J3/00
摘要： Disclosed is an integrated circuit comprising a substrate having a plurality of digital signal processors, including at least one analog circuit block, and means on said substrate for programmably interconnecting said processors and said at least one analog circuit block together. Also disclosed is a programming system comprising means for converting a programmable analog array specification into one or more programs executable by one or more digital signal processors so as to perform the identical or substantially identical function or functions as the programmed analog array.
摘要翻译：公开了一种集成电路，其包括具有多个数字信号处理器的基板，包括至少一个模拟电路块，以及在所述基板上的装置，用于可编程地将所述处理器和所述至少一个模拟电路块互连在一起。还公开了一种编程系统，其包括用于将可编程模拟阵列规格转换为可由一个或多个数字信号处理器执行的一个或多个程序，以便执行与所编程的模拟阵列相同或基本相同的功能或功能的装置。

14. 发明授权

US5630153A Integrated digital signal processor/general purpose CPU with shared internal memory 失效
标题翻译：集成数字信号处理器/通用CPU与共享内部存储器
公开(公告)号：US5630153A
公开(公告)日：1997-05-13
申请号：US317783
申请日：1994-10-04
申请人： Amos Intrater , Moshe Doron , Gideon Intrater , Lev Epstein , Maurice Valentaten , Israel Greiss
发明人： Amos Intrater , Moshe Doron , Gideon Intrater , Lev Epstein , Maurice Valentaten , Israel Greiss
IPC分类号： G06J3/00 , G06F9/38 , G06F15/78 , H04L27/00 , H04M11/00 , H04N1/40 , G06F9/26 , G06F9/40 , G06F9/44 , G06F13/36
CPC分类号： H04L27/00 , G06F15/7842 , G06F9/3885
摘要： An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose processor. The general purpose processor processes the digital data recovered by the DSP module, but is also available to perform general purpose tasks. A shared internal memory array selectively provides information to the DSP module and to the general purpose processor. The information stored in the internal memory array includes operands utilized in the execution of the DSP algorithm and selected instructions and data utilized by the general purpose CPU either for controlling the execution of the DSP algorithm or for executing its own general purpose tasks. While in many applications the data processing system will include an analog front end that converts a modulated input signal received on an analog transmission channel to a corresponding digital signal for processing by the data processing system, the data processing system may also receive the digital signal directly from a digital source.
摘要翻译：一种用于处理包括通用处理器和数字信号处理器（DSP）模块的数字信号的集成数据处理平台。 DSP模块利用通用处理器选择的一系列DSP操作，从数字信号中恢复数字数据。通用处理器处理由DSP模块恢复的数字数据，但也可用于执行通用任务。共享内部存储器阵列选择性地向DSP模块和通用处理器提供信息。存储在内部存储器阵列中的信息包括在DSP算法的执行中使用的操作数和通用CPU所使用的选择的指令和数据，用于控制DSP算法的执行或用于执行其自己的通用任务。在许多应用中，数据处理系统将包括模拟前端，将模拟传输通道上接收的调制输入信号转换为相应的数字信号，以供数据处理系统处理，数据处理系统也可以直接接收数字信号从数字来源。

15. 发明授权

US3522419A Electrical device for compensating a digital execution time in hybrid computer systems and the like 失效
标题翻译：用于补充混合计算机系统中的数字执行时间的电气设备和类似
公开(公告)号：US3522419A
公开(公告)日：1970-08-04
申请号：US3522419D
申请日：1968-05-01
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： MIURA TAKEO , IWATA JUNZO
IPC分类号： G06J1/00 , G06G7/18 , G06J3/00
CPC分类号： G06J1/00

16. 发明专利

JP2009037331A Information storage method using porphyrin metal complex 审中-公开
标题翻译：使用PORPHYRIN金属复合物的信息存储方法
公开(公告)号：JP2009037331A
公开(公告)日：2009-02-19
申请号：JP2007199590
申请日：2007-07-31
申请人： National Institute Of Information & Communication Technology , 独立行政法人情報通信研究機構
发明人： RYU KENKIN , MASUKO NOBURO
IPC分类号： G06N99/00 , G06J3/00
摘要： PROBLEM TO BE SOLVED: To provide an information storage method for storing information when calculating using a biochemical substance different form a DNA.
SOLUTION: This information storage method using a porphyrin metal complex includes: a step of preparing the finite types of porphyrin metal complexes; a step of determining positions 340 and 342 where the supermolecular structures of the porphyrin metal complexes are arranged on a prescribed metal face 320 in an order following information to be stored; and a step of, at the positions 340 and 342 following each section of the information to be stored on the prescribed metal face 320, forming the supermolecular structures configured of the porphyrin metal complexes having the structures following the sections.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种在使用不同于DNA的生物化学物质进行计算时存储信息的信息存储方法。解决方案：使用卟啉金属络合物的该信息存储方法包括：制备有限类型的卟啉金属络合物的步骤; 确定位置340和342的步骤，其中卟啉金属络合物的超分子结构按照要存储的信息的顺序排列在规定的金属面320上; 以及在要存储在规定的金属面320上的每个部分之后的位置340和342处的步骤，形成由具有这些部分之后的结构的卟啉金属络合物构成的超分子结构。版权所有（C）2009，JPO＆INPIT

17. 发明专利

JPH0769928B2 失效
公开(公告)号：JPH0769928B2
公开(公告)日：1995-07-31
申请号：JP50479290
申请日：1990-03-02
IPC分类号： G01D21/00 , G06F15/18 , G06J1/00 , G06J3/00 , G06N3/04 , G06N99/00 , G10L17/00 , H04L9/10 , H04L9/00 , H04L9/12

18. 发明专利

JPH06176180A MULTIPLIER CIRCUIT 失效
公开(公告)号：JPH06176180A
公开(公告)日：1994-06-24
申请号：JP35165092
申请日：1992-12-08
申请人： TAKAYAMA KK
发明人： UIWATSUTO UONWARAUIPATSUTO , YOU IKOU , KOTOBUKI KOKURIYOU , TAKATORI SUNAO , YAMAMOTO MAKOTO
IPC分类号： G06J3/00
摘要： PURPOSE:To enable direct multiplication between analog data and digital data by conducting the analog voltage which is level-compensated by an arithmetic amplifier and the output of the arithmetic amplifier by the switching of an electric-field effect transistor and inputting the digital data to the gate of the electric-field effect transistor. CONSTITUTION:A multiplier circuit M is provided with a pair of arithmetic amplifiers Amp3 and Amp4 and a pair of electromagnetic field effect transistors Tr3 and Tr4. Input analog data AX are inputted to the non-reverse input of the Amp3. The Tr3 is inputted to a gate and is conducted when the B is at high level. At the time of conducting the Tr3, the output of the Amp3 is adjusted to apply the same voltage as AX to the C4. Electric charges are stored in the C4 so that the charge voltage becomes AX. In the gate of the Tr4, digital data reversing B by the inverter INV are inputted. When the B is at a low level, the Tr4 is conducted. Thus, the multiplication between the analog data AX and the digital data is directly executed.

19. 实用新型

JPS5710059U 失效
公开(公告)号：JPS5710059U
公开(公告)日：1982-01-19
申请号：JP8295780
申请日：1980-06-16
IPC分类号： G06F15/02 , G06F1/00 , G06G1/00 , G06G1/06 , G06J3/00

20. 发明专利

JPS53108255A DIGITIZATION CONTROL DEVICE 失效
公开(公告)号：JPS53108255A
公开(公告)日：1978-09-20
申请号：JP2265477
申请日：1977-03-04
申请人： HITACHI LTD
发明人： MIYAZAKI TERUNOBU
IPC分类号： G06J3/00 , G06J1/00
摘要： PURPOSE:To achieve an economical digitization control device by securing an analog process for the arithmetic field such as the data integration or the calculation of a long-time average value in which a digital device is weak.

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