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11. 发明专利

JPS5613336B2 失效
公开(公告)号：JPS5613336B2
公开(公告)日：1981-03-27
申请号：JP7396878
申请日：1978-06-19
IPC分类号： G06F7/38 , G06F7/492 , G06F7/493 , G06F7/499 , G06F7/50 , G06F7/508 , G06F11/10

13. 发明专利

JPS5829539B2 失效
公开(公告)号：JPS5829539B2
公开(公告)日：1983-06-23
申请号：JP7337776
申请日：1976-06-23
申请人： INTAANASHONARU BIJINESU MASHIINZU CORP
发明人： DEBITSUDO ENU GUTSUDEINGU , EBARETSUTO EMU SHIMUPU
IPC分类号： G06F7/00 , G06F7/38 , G06F7/492 , G06F7/494 , G06F7/508 , G06F11/10 , H03M13/00

14. 发明公开

US20240012615A1 FAST MODULAR MULTIPLICATION OF LARGE INTEGERS 审中-公开
公开(公告)号：US20240012615A1
公开(公告)日：2024-01-11
申请号：US17811079
申请日：2022-07-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Silvia Melitta Mueller , Ulrich Mayer , Dominik Steenken , Yvo Thomas Bernard Mulder , Manoj Kumar
IPC分类号： G06F7/492 , G06F7/49 , G06F7/72 , G06F7/501
CPC分类号： G06F7/4925 , G06F7/49 , G06F7/725 , G06F7/501
摘要： In an approach, a processor receives a plurality of first operand values, where the first operand values are integer values. A processor adds, using binary addition, the plurality of first operand values resulting in a sum value S. A processor determines a single combined modular correction term D for a binary sum of all operand values based on leading bits of the sum value S. A processor performs a modular addition of S and D resulting in a modular sum of said plurality of said first operand values.

15. 发明申请

US20200334013A1 PROCESSING ELEMENT AND PROCESSING SYSTEM 审中-公开
公开(公告)号：US20200334013A1
公开(公告)日：2020-10-22
申请号：US16702099
申请日：2019-12-03
申请人： SK hynix Inc.
发明人： Jae-Hyeok JANG
IPC分类号： G06F7/492 , G06F7/50 , G06N3/063
摘要： A processing element may include a pre-processing circuit configured to receive and filter a feature and a weight and output a filtered feature and a filtered weight; and an accumulation circuit configured to accumulate a value of the filtered feature, wherein the pre-processing circuit comprises: a sign conversion circuit configured to change a sign of the feature and a sign of the weight when the weight having a value of −1; and a zero filtering circuit configured to change a value of the weight to 0 when the feature having a value of 0.

16. 发明公开

US20240013850A1 TECHNIQUES FOR ERROR MITIGATION TO IMPROVE RELIABILITY FOR ANALOG COMPUTE-IN-MEMORY 审中-公开
公开(公告)号：US20240013850A1
公开(公告)日：2024-01-11
申请号：US18372482
申请日：2023-09-25
申请人： Intel Corporation
发明人： Wei WU , Hechen WANG
IPC分类号： G11C29/52 , G11C7/18 , G06F7/492
CPC分类号： G11C29/52 , G11C7/18 , G06F7/4925
摘要： A compute-in-memory (CiM) circuit or structure arranged to detect errors. Examples include detecting errors associated with weight bits stored to computational nodes included in a CiM circuit or structure based on use of complimented bit values. Examples also include detecting errors in the CiM circuit or structure based on using at least some computational nodes included in an array of computational nodes to monitor for the errors during generation of computation results by other computational nodes included in the array.

17. 发明申请

US20210042088A1 CONDITION CODE ANTICIPATOR FOR HEXADECIMAL FLOATING POINT 有权
公开(公告)号：US20210042088A1
公开(公告)日：2021-02-11
申请号：US16536663
申请日：2019-08-09
申请人： International Business Machines Corporation
发明人： Silvia Melitta Mueller , Petra Leber , Kerstin Claudia Schelm , Cedric Lichtenau
IPC分类号： G06F7/499 , G06F7/492 , G06F7/483 , G06F9/30
摘要： An aspect includes executing, by a binary based floating-point arithmetic unit of a processor, a calculation having two or more operands in hexadecimal format based on a hexadecimal floating-point (HFP) instruction and providing a condition code for a calculation result of the calculation. The floating-point arithmetic unit includes a condition code anticipator circuit that is configured to provide the condition code to the processor prior to availability of the calculation result.

18. 发明专利

JP2554452B2 失效
公开(公告)号：JP2554452B2
公开(公告)日：1996-11-13
申请号：JP15194294
申请日：1994-07-04
申请人： INTAANASHONARU BIJINESU MASHIINZU CORP
发明人： SON DAOOTORON
IPC分类号： G06F7/499 , G06F7/492 , G06F7/493 , G06F7/50 , G06F7/507 , G06F7/508 , G06F11/16

19. 发明专利

JPH07295792A DECIMAL ADDER 失效
公开(公告)号：JPH07295792A
公开(公告)日：1995-11-10
申请号：JP8336094
申请日：1994-04-21
申请人： FUJITSU LTD
发明人： NAGATA TOSHIMITSU
IPC分类号： G06F7/50 , G06F7/492 , G06F7/494 , G06F7/508
摘要： PURPOSE:To establish various kinds of inspection functions and to improve reliability, constituting a decimal adder compactly and inexpensively by a system where an addition table is used for every figure, regarding the decimal adder performing the addition of data of BCD expression. CONSTITUTION:This adder performs an addition by separating each figure of the operand of a BCD expression into even-numbered components of upper 3 bits and odd-numbered component of lower 1 bit, performing addition processings for the even-numbered components, the odd-numbered components and the carry odd-numbered components, etc., for every figure and obtaining the sum for every figure and the carry odd-numbered component. The adder is composed by being provided with a parity correction means 15 correcting the parity of each operand to the parity according to the operand and the result of the addition processing based on the parity inversion information accompanied by the addition processing.

20. 发明专利

JPH0784760A SELF-CHECKING COMPLEMENT ADDER UNIT 失效
公开(公告)号：JPH0784760A
公开(公告)日：1995-03-31
申请号：JP15194294
申请日：1994-07-04
申请人： IBM
发明人： SON DAOOTORON
IPC分类号： G06F7/499 , G06F7/492 , G06F7/493 , G06F7/50 , G06F7/507 , G06F7/508 , G06F11/16
摘要： PURPOSE: To provide an adder which has a self-check function for high- performance subtraction by using a complementary adder. CONSTITUTION: The self-check type complementary adder unit consists of two carry selection adders (30 and 36) that have ripple carry adders (31 and 32 and also 37 and 38) respectively which consist of a pair of bytes or digits. A partial sum is selected from visual sums and makes a true sum by the signal which is generated by carry prefetch circuits (33 and 39). A multiplexer to which the output of both adders 30 and 36 is connected is controlled by a specific signal of the circuits 33 and 39 which show a symbol of a true sum. The multiplexer selects one of true sums as a result of subtraction. A sum check circuit compares parity bits of visual sums from both adders 30 and 36, also compares related signals which are sent from both adders 31 to 38 and from the circuits 33 and 39 and generates result check signals based on the results.

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