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11. 发明授权

US5434499A Constant current switching circuit provided with a base current compensating circuit 失效
标题翻译：具有基极电流补偿电路的恒流开关电路
公开(公告)号：US5434499A
公开(公告)日：1995-07-18
申请号：US159229
申请日：1993-11-30
申请人： Hiroshi Narikawa , Yoshiyuki Tamura
发明人： Hiroshi Narikawa , Yoshiyuki Tamura
IPC分类号： H03F3/343 , H03K17/62 , G05F3/16
CPC分类号： H03K17/6292
摘要： A current switching circuit has a setting section, a switching section and a switch changeover section. The switching section has a current mirror circuit, n switching transistors, and a compensating circuit. The current mirror circuit has first through third transistors. Emitters of the first and second transistors are connected to a power supply terminal and bases thereof are connected with each other. The third transistor has an emitter connected to the bases of the first and second transistors, a collector grounded, and a base connected to a collector of the first transistor. The switching transistors have emitters connected to the collector of the second transistor, and collectors connected to one terminals of n load elements. The other terminals of the load elements are grounded. The switch changeover section controls the base currents of the switching transistors. The compensating circuit comprises two compensating transistors. The first compensating transistor has an emitter and a base connected to an emitter and a base of the second transistor, respectively. The first compensating transistor has a same size as that of the second transistor. The second compensating transistor has an emitter connected to a collector of the first compensating transistor, a collector grounded, and a base connected to the collector of the second transistor. The second compensating transistor has a same size as that of each of the n switching transistors.
摘要翻译：电流开关电路具有设置部分，开关部分和开关切换部分。开关部分具有电流镜电路，n个开关晶体管和补偿电路。电流镜电路具有第一至第三晶体管。第一和第二晶体管的发射极连接到电源端子，其基极彼此连接。第三晶体管具有连接到第一和第二晶体管的基极的发射极，集电极接地，以及连接到第一晶体管的集电极的基极。开关晶体管具有连接到第二晶体管的集电极的发射极，以及连接到n个负载元件的一个端子的集电极。负载元件的其他端子接地。开关切换部分控制开关晶体管的基极电流。补偿电路包括两个补偿晶体管。第一补偿晶体管分别具有连接到第二晶体管的发射极和基极的发射极和基极。第一补偿晶体管具有与第二晶体管相同的尺寸。第二补偿晶体管具有连接到第一补偿晶体管的集电极，集电极接地的发射极和连接到第二晶体管的集电极的基极。第二补偿晶体管具有与n个开关晶体管中的每一个相同的尺寸。

12. 发明授权

US4727265A Semiconductor circuit having a current switch circuit which imparts a latch function to an input buffer for generating high amplitude signals 失效
标题翻译：具有电流开关电路的半导体电路，其向输入缓冲器提供锁存功能，用于产生高幅度信号
公开(公告)号：US4727265A
公开(公告)日：1988-02-23
申请号：US755910
申请日：1985-07-17
申请人： Hiroaki Nanbu , Noriyuki Honma , Kunihiko Yamaguchi , Kazuo Kanetani , Goro Kitsukawa
发明人： Hiroaki Nanbu , Noriyuki Honma , Kunihiko Yamaguchi , Kazuo Kanetani , Goro Kitsukawa
IPC分类号： G11C11/414 , G11C11/41 , H03K17/30 , H03K17/60 , H03K17/62 , H03K17/693 , H03K17/16 , H03K19/00 , H03K19/092 , H03L5/00
CPC分类号： H03K17/693 , H03K17/603 , H03K17/6292
摘要： A semiconductor circuit of a current mode type logic is provided having a reference voltage generating circuit which generates the reference voltage to be applied to the logic circuit in response to a clock signal to latch the state corresponding to an input signal at an instant of the clock signal input. The reference voltage has three levels in response to the voltage levels of the clock signal and the input signal: a middle voltage between the two high and low voltage levels of the input signal when the clock signal is at a first level voltage; a voltage higher than the high voltage level of the input signal when the clock signal is at a second level voltage and the output signal is at a high voltage; and a voltage lower than the low voltage level of the input signal when the clock signal is at a second level voltage and the output signal is at a second level voltage and the output signal is at a low voltage. This semiconductor circuit can relax restrictions on the signal amplitude due to the supply voltage and the saturation of the transistors, and, accordingly, allows processing signals having a much greater amplitude than was previously possible.
摘要翻译：提供电流模式型逻辑的半导体电路，其具有参考电压产生电路，该参考电压产生电路响应于时钟信号产生要施加到逻辑电路的参考电压，以在时钟瞬间锁存对应于输入信号的状态信号输入。参考电压响应于时钟信号和输入信号的电压电平而具有三个电平：当时钟信号处于第一电平电压时，输入信号的两个高电平和低电平电平之间的中间电压; 当所述时钟信号处于第二电平电压并且所述输出信号处于高电压时，所述电压高于所述输入信号的高电压电平; 以及当所述时钟信号处于第二电平电压并且所述输出信号处于第二电平电压且所述输出信号处于低电压时，所述电压低于所述输入信号的低电压电平。该半导体电路可以放宽由于晶体管的电源电压和饱和度导致的对信号幅度的限制，因此允许处理具有比之前可能的幅度大得多的信号。

13. 发明授权

US4608502A I.sup.2 L gate circuit arrangement having a switchable current source 失效
标题翻译： I2L门电路装置具有可切换的电流源
公开(公告)号：US4608502A
公开(公告)日：1986-08-26
申请号：US504199
申请日：1983-06-14
申请人： Eise C. Dijkmans , Wilhelm Graffenberger , Ernst A. Kilian
发明人： Eise C. Dijkmans , Wilhelm Graffenberger , Ernst A. Kilian
IPC分类号： H03K19/091 , H03F1/30 , H03F3/72 , H03G3/10 , H03K17/16 , H03K17/60 , H03K17/62 , H03K17/56 , H03K19/088
CPC分类号： H03K17/6292 , H03F1/305 , H03F3/72 , H03K17/16 , H03K17/602
摘要： The invention relates to a circuit arrangement having several signal paths which can be activated by a switchable current source. For the current source, use is made of I.sup.2 L gates whose injector connections are combined in two groups. When a switch-over is made from one signal path to another, a decreasing current is applied to the injector connection of the I.sup.2 L gate connected to one signal path while an increasing current is applied to the corresponding connection of the I.sup.2 L gate associated with the other signal path.
摘要翻译：本发明涉及具有若干信号路径的电路装置，其可被可切换的电流源激活。对于电流源，使用I2L门，其注入器连接组合在一起。当从一个信号路径切换到另一个信号路径时，减小的电流被施加到连接到一个信号路径的I2L门的注入器连接，而增加的电流被施加到与另一个相关联的I2L门的对应连接信号路径。

14. 发明授权

US09748951B2 Switching circuit 有权
公开(公告)号：US09748951B2
公开(公告)日：2017-08-29
申请号：US15195707
申请日：2016-06-28
申请人： IMEC VZW
发明人： Xiaoqiang Zhang , Mark Ingels
IPC分类号： H04L27/12 , H03K17/687 , H03F1/08 , H03F1/14 , H03F1/32 , H03F3/193 , H03F3/21 , H03F3/217 , H03F3/24 , H03M1/66 , H04L27/20 , H03K17/16 , H03K17/62 , H03M1/08 , H03M1/74
CPC分类号： H03K17/687 , H03F1/086 , H03F1/14 , H03F1/3205 , H03F3/193 , H03F3/211 , H03F3/2171 , H03F3/2178 , H03F3/245 , H03F2200/231 , H03F2200/324 , H03F2200/336 , H03F2200/451 , H03F2200/519 , H03F2200/525 , H03F2200/61 , H03F2200/75 , H03K17/161 , H03K17/164 , H03K17/6292 , H03M1/0863 , H03M1/66 , H03M1/742 , H04L27/20
摘要： A conversion circuit is disclosed. In one aspect, the conversion circuit includes a first input terminal for receiving a digital signal. The conversion circuit includes a second input terminal for receiving a bias voltage signal. The conversion circuit includes an output terminal for outputting a current. The conversion circuit includes a first and a second switch transistor connected to the first input terminal for receiving the digital signal. The conversion circuit includes a first and a second current source transistor connected to the second input terminal for receiving the bias voltage signal. The conversion circuit further includes a first branch, wherein the first switch transistor is connected to the output terminal via the first current source transistor. The conversion circuit further includes a second branch, wherein the second current source transistor is connected to the output terminal via the second switch transistor.

15. 发明申请

US20170005654A1 SWITCHING CIRCUIT 有权
标题翻译：切换电路
公开(公告)号：US20170005654A1
公开(公告)日：2017-01-05
申请号：US15195707
申请日：2016-06-28
申请人： IMEC VZW
发明人： Xiaoqiang Zhang , Mark Ingels
IPC分类号： H03K17/687 , H04L27/20 , H03M1/66
CPC分类号： H03K17/687 , H03F1/086 , H03F1/14 , H03F1/3205 , H03F3/193 , H03F3/211 , H03F3/2171 , H03F3/2178 , H03F3/245 , H03F2200/231 , H03F2200/324 , H03F2200/336 , H03F2200/451 , H03F2200/519 , H03F2200/525 , H03F2200/61 , H03F2200/75 , H03K17/161 , H03K17/164 , H03K17/6292 , H03M1/0863 , H03M1/66 , H03M1/742 , H04L27/20
摘要： A conversion circuit is disclosed. In one aspect, the conversion circuit includes a first input terminal for receiving a digital signal. The conversion circuit includes a second input terminal for receiving a bias voltage signal. The conversion circuit includes an output terminal for outputting a current. The conversion circuit includes a first and a second switch transistor connected to the first input terminal for receiving the digital signal. The conversion circuit includes a first and a second current source transistor connected to the second input terminal for receiving the bias voltage signal. The conversion circuit further includes a first branch, wherein the first switch transistor is connected to the output terminal via the first current source transistor. The conversion circuit further includes a second branch, wherein the second current source transistor is connected to the output terminal via the second switch transistor.
摘要翻译：公开了一种转换电路。一方面，转换电路包括用于接收数字信号的第一输入端。转换电路包括用于接收偏置电压信号的第二输入端。转换电路包括用于输出电流的输出端子。转换电路包括连接到第一输入端的第一和第二开关晶体管，用于接收数字信号。转换电路包括连接到第二输入端的第一和第二电流源晶体管，用于接收偏置电压信号。转换电路还包括第一分支，其中第一开关晶体管经由第一电流源晶体管连接到输出端子。转换电路还包括第二分支，其中第二电流源晶体管经由第二开关晶体管连接到输出端子。

16. 发明授权

US07135894B1 Dual-output current driver 有权
标题翻译：双输出电流驱动器
公开(公告)号：US07135894B1
公开(公告)日：2006-11-14
申请号：US10243240
申请日：2002-09-13
申请人： Marc Gerardus Maria Stegers , Rudolphe Gustave Hubertus Eschauzier
发明人： Marc Gerardus Maria Stegers , Rudolphe Gustave Hubertus Eschauzier
IPC分类号： H03K3/00
CPC分类号： H03K17/693 , H03K17/04106 , H03K17/04113 , H03K17/6292
摘要： A dual-output current driver includes a pair of output stages that provide output current to various devices such as LEDs and laser diodes. An output-stage selector circuit that includes a differential pair is arranged to activate one of the output stages at a time. A pair of push-pull circuits may be employed to drive the differential pair such that high speed switching is possible. A single-ended to differential conversion circuit controls the push-pull circuits. The selected output stage receives a drive current from a differential pair circuit in a current driver circuit. The current driver circuit includes another pair of push-pull circuits that drive its differential pair circuit, and one or more additional differential circuits that are arranged to activate the push-pull circuits. The various differential pair circuits in the current driver circuit can be arranged to provide phase reversal, or modulation of the drive current in the output stages.
摘要翻译：双输出电流驱动器包括一对输出级，其向诸如LED和激光二极管的各种器件提供输出电流。包括差分对的输出级选择器电路被布置成一次激活一个输出级。可以采用一对推挽电路来驱动差分对，使得高速切换成为可能。单端到差分转换电路控制推挽电路。所选择的输出级在当前驱动器电路中接收来自差分对电路的驱动电流。当前的驱动器电路包括驱动其差分对电路的另一对推挽电路，以及一个或多个附加差分电路，其被配置为启动推挽电路。电流驱动电路中的各种差分对电路可以被布置成提供相位反转或调制输出级中的驱动电流。

17. 发明授权

US4794275A Multiple phase clock generator 失效
标题翻译：多相时钟发生器
公开(公告)号：US4794275A
公开(公告)日：1988-12-27
申请号：US98110
申请日：1987-09-17
申请人： Einar O. Traa
发明人： Einar O. Traa
IPC分类号： H03H11/16 , H03K5/15 , H03K17/00 , H03K17/60 , H03K17/62 , H03L7/00 , H03K5/13 , H03K19/00 , H03K23/54
CPC分类号： H03K5/15073 , H03K17/007 , H03K17/603 , H03K17/6292
摘要： A multiple phase clock generator includes a ring of an even number of phase cells, each phase cell generating a separate phased clock signal. Each phase cell supplies its phased clock signal and a prebias output signal in response to concurrent assertion of an enable signal and a prebias output signal from a preceding phase cell on the ring. Enable signals supplied to each phase cell around the ring are asserted and deasserted in response to state changes in a master clock signal, enable signals supplied to non-adjacent phase cells being provided concurrently. When initialized with one phase cell asserting its phased clock signal and prebias output signal, each transition of the master clock signal causes a next phase cell on the ring to supply its phased clock output signal.

18. 发明授权

US4608503A Apparatus for driving first and second devices 失效
标题翻译：用于驱动第一和第二装置的装置
公开(公告)号：US4608503A
公开(公告)日：1986-08-26
申请号：US436762
申请日：1982-10-25
申请人： Thomas H. Wong , John W. Chu
发明人： Thomas H. Wong , John W. Chu
IPC分类号： H03K17/00 , H03K17/62 , H03K3/01 , H03K17/86
CPC分类号： H03K17/6292 , H03K2217/0036
摘要： A dual bus driver including a voltage input, a current source, a single data input, a first driver transistor for driving one bus, a second driver transistor for driving the other bus, a first pair of differential transistors for turning on either the first driver transistor or the second driver transistor to couple an input signal at the data input to the one bus or the other bus, and a second pair of differential transistors for disabling both driver transistors. By providing a driver that drives both buses, reduced power consumption, fewer circuit components and less integrated circuit layout complexities are achieved.
摘要翻译：一种双总线驱动器，包括电压输入，电流源，单个数据输入，用于驱动一个总线的第一驱动器晶体管，用于驱动另一个总线的第二驱动晶体管，第一对差分晶体管，用于接通第一驱动器晶体管或第二驱动器晶体管，以将数据输入处的输入信号耦合到一个总线或另一个总线;以及第二对差分晶体管，用于禁止两个驱动器晶体管。通过提供驱动两个总线的驱动器，降低功耗，实现更少的电路组件和更少的集成电路布局复杂性。

19. 发明专利

JPS59161005A Circuit element drive device 失效
标题翻译：电路元件驱动器件
公开(公告)号：JPS59161005A
公开(公告)日：1984-09-11
申请号：JP17946283
申请日：1983-09-29
申请人： Bosch Gmbh Robert
发明人： MACHIASU MERUBE
IPC分类号： H02J1/00 , B60T8/1761 , B60T8/36 , F16H61/02 , H01F7/18 , H01H47/00 , H03K17/62 , H03K17/64
CPC分类号： H03K17/64 , B60T8/17616 , B60T8/36 , F16H61/0251 , H01F7/1877 , H03K17/6292

20. 发明专利

JPS6129213A Semiconductor circuit 失效
标题翻译：半导体电路
公开(公告)号：JPS6129213A
公开(公告)日：1986-02-10
申请号：JP14937084
申请日：1984-07-20
申请人： Hitachi Ltd
发明人： NANBU HIROAKI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , KITSUKAWA GORO
IPC分类号： G11C11/414 , G11C11/41 , H03K17/30 , H03K17/60 , H03K17/62 , H03K17/693
CPC分类号： H03K17/693 , H03K17/603 , H03K17/6292
摘要： PURPOSE: To enable to handle signals of large amplitude in a semiconductor circuit provided with a current switching circuit, by generating specified three kinds of reference potential.
CONSTITUTION: When taking in an input signal VIN
1 , it is enough to generate intermediate potential VBB(M) between high potential VIN
1 (H) and low potential VIN
1 (L) of the input signal. At this time, if the input signal is VIN
1 (H), a transistor TRQ1 becomes on, and if VIN
1 (L), TRQ2 becomes on. When the input signal is not to be taken in, reference potential VBB(L) lower than low potential VIN
1 (L) of the input signal or reference potential VBB(H) higher than high potential VIN
1 (H) is to be generated. Under this state, TRQ1 or Q2 always become on regardless of the level of the input signal VIN
1 . Thus, signals of large amplitude can be handled.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过产生指定的三种参考电位，能够处理具有电流开关电路的半导体电路中的大幅度信号。构成：当输入信号VIN1时，足以在输入信号的高电位VIN1（H）和低电位VIN1（L）之间产生中间电位VBB（M）。此时，如果输入信号为VIN1（H），则晶体管TRQ1导通，如果VIN1（L），TRQ2导通。当不输入输入信号时，将产生低于高电平VIN1（H）的输入信号或参考电位VBB（H）的低电位VIN1（L）的参考电位VBB（L）。在这种状态下，无论输入信号VIN1的电平如何，TRQ1或Q2总是导通。因此，可以处理大振幅的信号。

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