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11. 发明申请

WO8500077A2 SELF-ALIGNED GATE MESFET AND THE METHOD OF FABRICATING SAME 审中-公开
标题翻译：自对准的门式绝缘体及其制造方法
公开(公告)号：WO8500077A2
公开(公告)日：1985-01-03
申请号：PCT/US8400759
申请日：1984-05-18
申请人： HUGHES AIRCRAFT CO
发明人： LEE ROBERT E , LEVY HAROLD M
IPC分类号： H01L21/302 , H01L21/265 , H01L21/318 , H01L21/338 , H01L29/423 , H01L29/47 , H01L29/80 , H01L29/812
CPC分类号： H01L29/66848 , H01L21/3185 , H01L29/42316 , H01L29/475 , H01L29/66878 , H01L29/812
摘要： An improved performance MESFET device incorporating a structure fabricated utilizing self-aligned gate process technology. The edges of the gate electrode (28) formed are separated from the edges (23, 25) of the dopant regions (26, 27) implanted in the device substrate (23) by a distance which optimizes device performance. In order to increase process yield, a layer of dielectric material (29) is deposited on the substrate surface and then annealed to protect the gate electrode and both stabilize and planarize the substrate surface.
摘要翻译：一种改进的性能MESFET器件，其结合使用自对准栅极工艺技术制造的结构。所形成的栅电极（28）的边缘与植入器件衬底（23）中的掺杂剂区域（26,27）的边缘（23,25）分开一定距离，其优化器件性能。为了提高工艺成品率，将一层电介质材料（29）沉积在衬底表面上，然后退火以保护栅电极并稳定和平坦化衬底表面。

12. 发明专利

JP4751498B2 Semiconductor three-terminal device 有权
公开(公告)号：JP4751498B2
公开(公告)日：2011-08-17
申请号：JP2000095895
申请日：2000-03-30
申请人：富士通株式会社
发明人：瑞久二瓶 , 祐渡邊
IPC分类号： H01L21/28 , H01L21/338 , H01L21/283 , H01L21/285 , H01L21/335 , H01L29/201 , H01L29/417 , H01L29/47 , H01L29/778 , H01L29/812
CPC分类号： H01L29/66878 , H01L21/28587 , H01L29/475 , H01L29/66462 , H01L29/7783 , H01L29/812

13. 发明专利

JPS61117869A Manufacture of fet 失效
标题翻译： FET的制造
公开(公告)号：JPS61117869A
公开(公告)日：1986-06-05
申请号：JP23852084
申请日：1984-11-14
申请人： Toshiba Corp
发明人： MURATA EIJI , YAMAGISHI HARUO
IPC分类号： H01L29/812 , H01L21/285 , H01L21/338 , H01L29/423
CPC分类号： H01L29/66878 , H01L21/28587 , H01L29/42316
摘要： PURPOSE:To unnecessitate the process of precise mask alignment, and to contrive to secure the gate-source withstand voltage and to improve the controllability and uniformity of the gate length, by a method wherein a gate electrode is formed by self-alignment with source-drain electrodes, and the source-drain electrodes are formed by self-alignment with source-drain regions. CONSTITUTION:The titled device is made of the nitride or silicide of a transition metal excellent in thermal stability. A T-type gate 301 is obtained by side- etching the first metallic layer 3. Next, high concentration ion-implanted regions 8, 9 are obtained by implanting ions 7 serving as the N type impurity with the mask of the T-type gate 301 and the second insulation film 35 on its side wall; thereafter, a source region 18 and a drain region 19 are obtained by heat treatment. Then, an ohmic metallic layer 104 is adhered, and a source electrode 38 and a drain electrode 39 are formed, thereby obtaining a FET113 having the T-type gate.
摘要翻译：目的：为了不需要精确的掩模对准的过程，并且通过其中栅电极通过与源极保护的自对准形成的方法，并且旨在确保栅极 - 源极耐受电压并提高栅极长度的可控性和均匀性，漏极电极和源极 - 漏极电极通过与源极 - 漏极区域的自对准形成。构成：标准装置由热稳定性优异的过渡金属的氮化物或硅化物制成。通过侧蚀第一金属层3获得T型栅极301.接下来，通过用T型栅极的掩模注入用作N型杂质的离子7，获得高浓度离子注入区域8,9 301，第二绝缘膜35在其侧壁上; 此后，通过热处理获得源区18和漏区19。然后，粘附欧姆金属层104，形成源电极38和漏电极39，从而获得具有T型栅极的FET113。

14. 发明专利

JPS59124172A Conductor structure 失效
标题翻译：导体结构
公开(公告)号：JPS59124172A
公开(公告)日：1984-07-18
申请号：JP14679783
申请日：1983-08-12
申请人： Ibm
发明人： TOOMASU NERUSON JIYAKUSON
IPC分类号： H01L29/812 , H01L21/033 , H01L21/265 , H01L21/28 , H01L21/285 , H01L21/338 , H01L29/417
CPC分类号： H01L29/66878 , H01L21/0337 , H01L21/26586 , H01L21/2815

15. 发明专利

JPS61108175A Semiconductor device and manufacture thereof 失效
标题翻译：半导体器件及其制造
公开(公告)号：JPS61108175A
公开(公告)日：1986-05-26
申请号：JP22900484
申请日：1984-11-01
申请人： Toshiba Corp
发明人： SHIMADA CHO , AKIYAMA TATSUO , ETSUNO YUTAKA
IPC分类号： H01L21/338 , H01L29/812 , H01L29/80
CPC分类号： H01L29/66878 , H01L29/812
摘要： PURPOSE: To obtain an MESFET having excellent characteristics at a high yield rate, by determining the intervals between a gate electrode, a source and a drain based on the thickness of the film of plasma CVD SiO
2 on the side surface of the gate electrode, and using the film on the upper surface of the gate electrode for the lift-off of an ohmic metal film.
CONSTITUTION: On an N
- layer 1A of a GaAs substrate 1, three-layer upright piece 16 comprising Mo 12, Au 13 and SiO
2 14 is selectively formed. The surface is covered by P-SiO
2 17 by a plasma CVD method. A resist mask 18 is provided, and N
+ ion implanted layer 1B is formed. RIE is performed, and the film on the N
+ layer 1B and the upright body 16 is removed. The surface is covered by an ohmic metal film 20, in which Ni is overlapped on AuGe. After heat treatment, the SiO
2 17 and 14 are melted and removed, and source and drain electrodes 21 and 22 are obtained. In this constitution, the ohmic electrodes 21 and 22, which are aligned with the N
+ layer, are obtained, the intervals between the gate electrode 23, the source 24 and the drain 25 are precisely set, and the device characterized by the lower source series resistance and excellent withstanding voltage, can be obtained.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过基于栅电极的侧表面上的等离子体CVD SiO 2的膜的厚度确定栅电极，源极和漏极之间的间隔，以高产率获得具有优异特性的MESFET，以及使用在栅电极的上表面上的薄膜用于欧姆金属膜的剥离。构成：在GaAs衬底1的N +层1A上，选择性地形成包括Mo 12，Au 13和SiO 2 14的三层直立件16。通过等离子体CVD法，表面被P-SiO 2 17覆盖。设置抗蚀剂掩模18，形成N +离子注入层1B。执行RIE，并且去除N +层1B和直立体16上的膜。表面被欧姆金属膜20覆盖，其中Ni与AuGe重叠。热处理后，熔融并除去SiO 2 17和14，得到源电极21和漏电极22。在这种结构中，获得与N +层对准的欧姆电极21和22，栅电极23，源24和漏极25之间的间隔被精确地设定，可以获得较低的源极串联电阻和优异的耐受电压。

16. 发明专利

JPS6182482A Manufacture of gaas field effect transistor 失效
标题翻译： GAAS场效应晶体管的制作
公开(公告)号：JPS6182482A
公开(公告)日：1986-04-26
申请号：JP20441684
申请日：1984-09-29
申请人： Toshiba Corp
发明人： TERADA TOSHIYUKI
IPC分类号： H01L21/033 , H01L21/28 , H01L21/285 , H01L21/302 , H01L21/3065 , H01L21/338 , H01L29/812
CPC分类号： H01L29/66878 , H01L21/0337 , H01L21/2815 , H01L21/28587 , H01L21/28593 , H01L29/812
摘要： PURPOSE: To obtain a GaAsFET having small resistance between a gate and a source and a high drain withstand voltage in a self-aligning manner by forming a source region near a gate electrode, and forming a drain region separated at the prescribed distance from the gate electrode.
CONSTITUTION: Si
+ ions are implanted to a semi-insulating GaAs substrate 11 to form an operating layer 12, an SiO
2 film 13 is accumulated, etched by a reactive ion etching (RIE) method, and the side wall is formed perpendicular with respect to the substrate 11. A WSi
2 film 14 is formed, a WSi
2 film 14 remains as a gate electrode on the film 13 side wall. The film 13 is removed, an SiO
2 film 15 is accumulated, and the film 15 remains on the side of the film 14 by the RIE. With the gate electrode 14 and the film 15 as masks Si
+ ions are implanted a source region 16 is formed near the electrode 14, a drain region 17 is separated in the width of the film 15, and a source electrode 18 of AuGe alloy and a drain electrode 19 are then formed.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过在栅电极附近形成源极区域，以自对准方式获得栅极和源极之间的电阻较小的漏极耐受电压，并形成与栅极隔开规定距离的漏极区域电极。构成：将Si +离子注入到半绝缘GaAs衬底11中以形成操作层12，通过反应离子蚀刻（RIE）方法积聚SiO 2膜13，蚀刻，并且侧壁垂直于相对于基板11.形成WSi2膜14，WSi2膜14作为栅电极保留在膜13侧壁上。去除膜13，积聚SiO 2膜15，并且膜15通过RIE保留在膜14的侧面上。在栅电极14和膜15作为掩模Si +离子的情况下，在电极14附近形成源极区16，漏极区17在膜15的宽度上分离，AuGe的源电极18 合金和漏电极19。

17. 发明专利

JPS57126168A Schottky gate field effect transistor 失效
标题翻译：肖特基门场效应晶体管
公开(公告)号：JPS57126168A
公开(公告)日：1982-08-05
申请号：JP1181281
申请日：1981-01-29
申请人： Sumitomo Electric Ind Ltd
发明人： KIKUCHI KENICHI
IPC分类号： H01L29/80 , H01L21/338 , H01L29/10 , H01L29/47 , H01L29/812
CPC分类号： H01L29/66871 , H01L29/1029 , H01L29/475 , H01L29/66878 , H01L29/812
摘要： PURPOSE:To obtain a Schottky gate field effect transistor having favorable microwave characteristic by a method wherein an operational layer having the flat surface is formed on a semiinsulating semiconductor substrate by ion implan tation, a mask is provided at the center part, ions are implanted again to the part of the operational layer wherein the mask is not exist to enhance concentration of carriers and to make depth thereof to deeper, a gate pole is provided at the center part, and source and drain poles are provided at both the end parts. CONSTITUTION:An operational layer 22' having uniform thickness is formed by Si ion implantation on the surface of a semiinsulating GaAs substrate 21 selecting thickness and concentration of carriers as to enable to obtain the desired pinch off voltage. Then the pattern 27 of photo resist film is provided at the center part thereon, ion implantation is performed again making the film thereof as the mask, and the operational layer 22'' being added with concentration of carriers deeper than the operational layer 22' is made to be generated at the region wherein the pattern 27 does not exist. After then, the pattern 27 is removed, the gate pole 25 is equipped thereto, and the source pole 23 and the drain pole 24 are formed respectively at both the end parts of the operational layer 22'' interposign the gate pole between them.
摘要翻译：目的：通过一种方法获得具有良好微波特性的肖特基门场效应晶体管，其中通过离子注入在半绝缘半导体衬底上形成具有平坦表面的操作层，在中心部分设置掩模，再次注入离子对于其中不存在掩模以增强载流子浓度并使其深度更深的操作层的部分，在中心部分设置栅极，并且在两个端部设置源极和漏极。构成：在半绝缘GaAs衬底21的表面上通过Si +离子注入形成具有均匀厚度的操作层22'，其选择载流子的厚度和浓度，以便能够获得所需的夹断电压。然后在其中心部分设置光致抗蚀剂膜的图案27，再次进行离子注入，使其膜为掩模，加上深于工作层22'的载流子浓度的工作层22“为使其在图案27不存在的区域产生。之后，去除图案27，配备栅极25，并且分别在操作层22“的两端的两个端部形成源极23和漏极24”，这两个端极在它们之间插入栅极。

18. 发明专利

JP2011249728A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011249728A
公开(公告)日：2011-12-08
申请号：JP2010124295
申请日：2010-05-31
申请人： Toshiba Corp , 株式会社東芝
发明人： MIYAO AKIO
IPC分类号： H01L21/338 , H01L21/28 , H01L29/41 , H01L29/417 , H01L29/812
CPC分类号： H01L29/806 , H01L29/20 , H01L29/404 , H01L29/66878
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which a gate parasitic capacitance component Cgs between a gate electrode and a source electrode can be reduced.SOLUTION: A semiconductor device comprises: an operation layer 12 formed on a semiconductor substrate 11; a drain electrode 13 and source electrode 14 formed so as to be spaced apart from each other on a surface of the operation layer 12; a gate electrode 15 formed between the drain electrode 13 and the source electrode 14 on the surface of the operation layer 12; a surface protection film 19 formed between the drain electrode 13 and the source electrode 14 so as to cover the gate electrode 15 on the surface of the operation layer 12; a source field plate electrode 20 formed at a position overhanging at least an end portion of the gate electrode 15 on a drain side on a surface of the surface protection film 19; and a plurality of wiring lines 21 formed on the surface protection film 19, the plurality of wiring lines being electrically connected to the source field plate electrode 20 and the source electrode 14 and being smaller in width than the electrodes 20 and 14.
摘要翻译：要解决的问题：提供可以减小栅电极和源电极之间的栅极寄生电容分量Cgs的半导体器件。解决方案：半导体器件包括：形成在半导体衬底11上的操作层12; 形成为在操作层12的表面上彼此间隔开的漏电极13和源电极14; 在操作层12的表面上形成在漏电极13和源电极14之间的栅电极15; 形成在漏电极13和源电极14之间的表面保护膜19，以覆盖操作层12的表面上的栅电极15; 源极场电极20，形成在表面保护膜19的表面上的漏极侧的至少一个端电极15的端部悬伸的位置; 以及形成在表面保护膜19上的多条布线21，多条布线与源场极板电极20和源电极14电连接，宽度小于电极20和14。版权所有（C）2012，JPO＆INPIT

19. 发明专利

JP2005051265A Iii-v semiconductor gate structure and manufacturing method of the same 审中-公开
标题翻译： III-V半导体门结构及其制造方法
公开(公告)号：JP2005051265A
公开(公告)日：2005-02-24
申请号：JP2004279032
申请日：2004-09-27
申请人： Motorola Inc , モトローラ・インコーポレイテッドMotorola Incorporated
发明人： CHO JAESHIN , KYLER KELLY W , CRONIN WAYNE A , DURLAM MARK , JONATHAN K ABUROKUWA
IPC分类号： H01L21/28 , H01L21/033 , H01L21/283 , H01L21/338 , H01L29/812
CPC分类号： H01L29/66878 , H01L21/0337 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a III-V semiconductor gate structure and a manufacturing method of the same.
SOLUTION: A silicon nitride layer 12 is formed on a III-V semiconductor material 10, and a dielectric layer 13 including aluminum is formed on the silicon nitride layer 12. Then, another dielectric layer 14 including silicon and oxygen is formed on the dielectric layer 13 including the aluminum. The dielectric layer 13 including aluminum acts as a stop layer for etching the dielectric layer 14 including silicon and oxygen by a high output reactive ion etching. Next, by using a wet etching agent that does not substantially etch the silicon nitride layer 12, the dielectric layer 13 including aluminum is etched. By forming the dielectric layer 13 including aluminum between the silicon nitride layer 12 and the dielectric layer 14 including silicon and oxygen, the damage on the surface of the semiconductor material 10 by exposure to the high output reactive ion etching is prevented.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供III-V半导体栅极结构及其制造方法。解决方案：在III-V半导体材料10上形成氮化硅层12，并且在氮化硅层12上形成包括铝的电介质层13.然后，在另一个包含硅和氧的电介质层14上形成包括铝的电介质层13。包括铝的电介质层13用作通过高输出反应离子蚀刻来蚀刻包括硅和氧的电介质层14的停止层。接下来，通过使用基本上不蚀刻氮化硅层12的湿蚀刻剂，蚀刻包括铝的电介质层13。通过在氮化硅层12和包含硅和氧的电介质层14之间形成包括铝的电介质层13，可以防止通过暴露于高输出反应离子蚀刻对半导体材料10的表面的损坏。版权所有（C）2005，JPO＆NCIPI

20. 发明专利

JP3501284B2 A method of manufacturing a semiconductor device 有权
公开(公告)号：JP3501284B2
公开(公告)日：2004-03-02
申请号：JP2001101443
申请日：2001-03-30
申请人：富士通カンタムデバイス株式会社
发明人：浩遠藤
IPC分类号： H01L29/41 , H01L21/331 , H01L21/338 , H01L29/737 , H01L29/812
CPC分类号： H01L29/66878 , H01L29/66318 , H01L29/7371

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