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11. 发明申请

WO2003092151A1 DEMODULATOR USING DIGITAL CIRCUITRY 审中-公开
标题翻译：使用数字电路的DEMODULATOR
公开(公告)号：WO2003092151A1
公开(公告)日：2003-11-06
申请号：PCT/US2003/012806
申请日：2003-04-25
申请人： CELIS SEMICONDUCTOR CORPORATION
发明人： DEVILBISS, Alan, D.
IPC分类号： H03D3/00
CPC分类号： H03D3/04
摘要： A demodulator (3) converts a voltage input "VIN" to an output voltage. The demodulator (3) has a voltage-controlled oscillator (6), a counter (21), a holding apparatus (22). The VCO (6) generates a signal having a frequency proportional to the analog input voltage "VIN". The counter (21) counts each cycle of the signal generated by the VCO (6) and outputs a count signal representative of the cycle count. The holding apparatus (22) holds the count signal and generates a held count signal. The digital compare apparatus (23) compares the count signal and the held count signal and generates the digital output (42).
摘要翻译：解调器（3）将电压输入“VIN”转换为输出电压。解调器（3）具有压控振荡器（6），计数器（21），保持装置（22）。 VCO（6）产生具有与模拟输入电压“VIN”成比例的频率的信号。计数器（21）计算由VCO（6）产生的信号的每个周期，并输出表示循环计数的计数信号。保持装置（22）保持计数信号并产生保持的计数信号。数字比较装置（23）比较计数信号和保持的计数信号，并产生数字输出（42）。

12. 发明公开

EP1119861A1 SELF-REFERENCING FERROELECTRIC MEMORY 审中-公开
标题翻译：具有自调整参考FERRO电记忆
公开(公告)号：EP1119861A1
公开(公告)日：2001-08-01
申请号：EP99952031.5
申请日：1999-10-13
申请人： Celis Semiconductor Corporation
发明人： KAMP, David, A.
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric integrated circuit memory (436) includes a memory cell (110) having a ferroelectric capacitor (112), one electrode (120) of which is connected to a bit line (130) through a transistor (114) and the other electrode (122) of which is connected to a plate line (132). The plate line is floating at one-half Vcc when the bit line is lowered to zero volts to develop a read voltage on the plate line. A unity gain amplifier (106) then drives a complementary plate line (131) to the same voltage as the plate line, then the plate line and complementary plate line are connected via a transistor (156), and the bit line is raised to Vcc to develop a reference voltage. This operation subtracts the read voltage from the reference voltage to develop a net voltage on the complementary plate line. The voltage on the complementary plate line is applied to an output line (158), compared via a sense amplifier (108) to a one-half Vcc voltage on an input line (157), and the sense amp then drives the input and output lines to zero and Vcc, depending on whether the developed voltage was greater or less than one-half Vcc.

13. 发明公开

EP1509999A1 DEMODULATOR USING DIGITAL CIRCUITRY 有权
标题翻译：解调器使用数字电路
公开(公告)号：EP1509999A1
公开(公告)日：2005-03-02
申请号：EP03738879.0
申请日：2003-04-25
申请人： Celis Semiconductor Corporation
发明人： DEVILBISS, Alan, D.
IPC分类号： H03D3/00
CPC分类号： H03D3/04
摘要： A demodulator (3) converts a voltage input 'VIN' to an output voltage. The demodulator (3) has a voltage-controlled oscillator (6), a counter (21), a holding apparatus (22). The VCO (6) generates a signal having a frequency proportional to the analog input voltage 'VIN'. The counter (21) counts each cycle of the signal generated by the VCO (6) and outputs a count signal representative of the cycle count. The holding apparatus (22) holds the count signal and generates a held count signal. The digital compare apparatus (23) compares the count signal and the held count signal and generates the digital output (42).

14. 发明公开

EP1508162A2 METHOD FOR PRODUCING AN ELECTRICAL CIRCUIT 审中-公开
标题翻译：方法制造电路
公开(公告)号：EP1508162A2
公开(公告)日：2005-02-23
申请号：EP03747317.0
申请日：2003-04-25
申请人： Celis Semiconductor Corporation
发明人： DERBENWICK, Gary, F. , DEVILBISS, Alan, D.
IPC分类号： H01L21/00
CPC分类号： H05K1/186 , G06K19/07749 , H01L23/49833 , H01L2224/16 , H05K1/189 , H05K2201/055
摘要： An electrical circuit is formed by forming and patterning a conductive layer on a substrate (1), forming and patterning a conductive layer on another substrate (40), depositing a dielectric layer (37) on at least a portion of one of conductive layers (3, 41), mounting an integrated (5) circuit (IC) between the substrates, coupling the IC to the conductive layers, and affixing the substrates together with the conductive layers between the substrates. These are either separate substrates or a unitary substrate. The IC is mounted either to a substrate, a conductive layer, or a dielectric layer. The IC is coupled to the conductive layers either directly or through openings formed in the dielectric layer. An interior conductive layer may be used to couple the IC to the conductive layers.

15. 发明授权

EP1509999B1 DEMODULATOR USING DIGITAL CIRCUITRY 有权
标题翻译：解调器使用数字电路
公开(公告)号：EP1509999B1
公开(公告)日：2006-10-25
申请号：EP03738879.0
申请日：2003-04-25
申请人： Celis Semiconductor Corporation
发明人： DEVILBISS, Alan, D.
IPC分类号： H03D3/00 , H03D3/04 , H03D1/04
CPC分类号： H03D3/04
摘要： A demodulator (3) converts a voltage input "VIN" to an output voltage. The demodulator (3) has a voltage-controlled oscillator (6), a counter (21), a holding apparatus (22). The VCO (6) generates a signal having a frequency proportional to the analog input voltage "VIN". The counter (21) counts each cycle of the signal generated by the VCO (6) and outputs a count signal representative of the cycle count. The holding apparatus (22) holds the count signal and generates a held count signal. The digital compare apparatus (23) compares the count signal and the held count signal and generates the digital output (42).

16. 发明公开

EP1509986A2 RECTIFIER UTILIZING A GROUNDED ANTENNA 审中-公开
标题翻译：带有接地天线整流器
公开(公告)号：EP1509986A2
公开(公告)日：2005-03-02
申请号：EP03717959.5
申请日：2003-03-12
申请人： Celis Semiconductor Corporation
发明人： DEVILBISS, Alan, D. , DERBENWICK, Gary, F.
IPC分类号： H02J9/00
CPC分类号： G06K19/0775 , G06K19/0701 , G06K19/0715 , G06K19/0723 , G06K19/07749
摘要： A rectifier (diodes, 30, 32) generates a rectified output and a do power output (22). The rectifier has an antenna element (24), a tuning capacitor (26), a coupling capacitor (28), first (30) and second (32) rectifying diodes, and a storage capacitor (34). The antenna element (24) and the tuning capacitor (26) are coupled in parallel and grounded at one terminal. The first rectifying diode (30) is grounded at its anode terminal and the storage capacitor (34) is grounded at one terminal. The coupling capacitor (30) is coupled between the ungrounded terminal of the antenna element (24) and the cathode terminal of the first rectifying diode 30). The anode terminal of the second rectifying diode (32) is coupled to the cathode terminal of the first rectifying diode (30). The cathode terminal of the second rectifying diode (32) is coupled to the ungrounded terminal of the storage capacitor (34). The rectifying output is generated between the rectifying diodes (node 20). The dc power output is generated between the second rectifying diode (32) and the storage capacitor (node 22).

17. 发明公开

EP1490852A1 INTEGRATED CIRCUIT WITH ENHANCED COUPLING 审中-公开
标题翻译：具有改进的耦合集成电路
公开(公告)号：EP1490852A1
公开(公告)日：2004-12-29
申请号：EP03716470.4
申请日：2003-03-12
申请人： Celis Semiconductor Corporation
发明人： DE VILBISS, Alan, D.
IPC分类号： G08B13/14
CPC分类号： G08B13/2414 , G06K7/0008 , G06K7/10178 , G06K19/07756 , G08B13/2417 , G08B13/2448
摘要： A system for conveying a radio frequency (RF) signal from a base station (16) to a detached integrated circuit (IC) has an intermediate resonant circuit (4) and an IC (2). The intermediate resonant circuit is configured to resonate in response to the RF signal from the base station, reproducing the RF signal. The IC has an integral resonant circuit (6, 8, 10) configured to resonate in response to the reproduced RF signal. The IC and the intermediate resonant circuit are affixed proximate each other. Both are separate from the base station and each other. Either or both of the intermediate resonant circuit and the integral resonant circuit may contact a high magnetic permeability layer. The intermediate resonant circuit may be formed of conductive ink.

18. 发明公开

EP1127354A1 FERROELECTRIC MEMORY WITH INCREASED SWITCHING VOLTAGE 审中-公开
标题翻译：具有增强的开关电压FERRO电记忆
公开(公告)号：EP1127354A1
公开(公告)日：2001-08-29
申请号：EP99956834.8
申请日：1999-11-02
申请人： Celis Semiconductor Corporation
发明人： DERBENWICK, Gary, F. , KAMP, David, A. , CORDOBA, Michael , COOMBE, George, B.
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric integrated circuit memory (18, 436) includes a memory cell (17, 70, 210) having a ferroelectric capacitor (76, 212, 214), one electrode (20, 211, 217) of which is connected to a bit line (79, 220, 222) through a transistor (78, 202, 203), and the other electrode (22, 213, 215) of which is connected to a plate line (85, 224). The bit line is also connected to system ground (11, 112, 261, 262) through a precharge transistor (110, 252, 253). In a read cycle, the precharge transistor remains on after the word line (86, 221) goes high connecting the capacitor to the bit line. At least a portion of the linear displacement current that flows to the bit line is drained off to ground via the precharge transistor, thereby increasing the switching voltage across the ferroelectric capacitor. The precharge transistor is turned off before or during the switching of the ferroelectric capacitor. The signal applied to the gate (108, 258, 259) of the precharge transistor is boosted above the supply voltage of the memory to shorten the cycle time.

19. 发明授权

US07078304B2 Method for producing an electrical circuit 失效
标题翻译：电路制造方法
公开(公告)号：US07078304B2
公开(公告)日：2006-07-18
申请号：US11098738
申请日：2005-04-04
申请人： Gary F. Derbenwick , Alan D. DeVilbiss
发明人： Gary F. Derbenwick , Alan D. DeVilbiss
IPC分类号： H01L21/8222
CPC分类号： H05K1/186 , G06K19/07749 , H01L23/49833 , H01L2224/16 , H05K1/189 , H05K2201/055
摘要： An electrical circuit is formed by forming and patterning a conductive layer on a substrate, forming and patterning a conductive layer on another substrate, depositing a dielectric layer on at least a portion of one of conductive layers, mounting an integrated circuit (IC) between the substrates, coupling the IC to the conductive layers, and affixing the substrates together with the conductive layers between the substrates. These are either separate substrates or a unitary substrate. The IC is mounted either to a substrate, a conductive layer, or a dielectric layer. The IC is coupled to the conductive layers either directly or through openings formed in the dielectric layer. An interior conductive layer may be used to couple the IC to the conductive layers.
摘要翻译：通过在衬底上形成和图案化导电层形成电路，在另一个衬底上形成和构图导电层，在导电层的至少一部分上沉积介电层，将集成电路（IC）安装在衬底，将IC耦合到导电层，以及将衬底与导电层粘合在衬底之间。这些是单独的基底或单一基底。 IC安装在基板，导电层或电介质层上。 IC直接地或通过形成在电介质层中的开口耦合到导电层。内部导电层可以用于将IC耦合到导电层。

20. 发明授权

US07542315B2 Active rectifier 失效
标题翻译：有源整流器
公开(公告)号：US07542315B2
公开(公告)日：2009-06-02
申请号：US11564932
申请日：2006-11-30
申请人： Alan D. DeVilbiss
发明人： Alan D. DeVilbiss
IPC分类号： H02M5/42 , H02M7/04 , H02M7/68
CPC分类号： H02M7/217
摘要： A voltage signal rectifier produces a rectified voltage signal from an input offset voltage signal. The voltage signal rectifier includes input offset, output, and reference nodes, two actively controlled current regulation elements (ACCREs), and two controllers. The input offset node is coupled to the input offset voltage signal. The rectified voltage signal is generated onto the output node. The reference node is coupled to a reference voltage for the input offset and rectified voltage signals. The ACCREs are coupled to the input offset node and one of the ACCREs is coupled to the output node. Each controller is configured to control the one of the ACCREs so that the ACCRE coupled to the output node allows current flow through it when the input offset voltage signal is higher than the rectified voltage signal and the other ACCRE is configured to allows current flow through it when the input offset voltage signal is lower than the rectified voltage signal.
摘要翻译：电压信号整流器从输入偏移电压信号产生整流电压信号。电压信号整流器包括输入偏移，输出和参考节点，两个主动控制的电流调节元件（ACCRE）和两个控制器。输入偏移节点耦合到输入偏移电压信号。整流电压信号被产生到输出节点上。参考节点耦合到用于输入偏移和整流电压信号的参考电压。 ACCRE耦合到输入偏移节点，并且ACCRE中的一个耦合到输出节点。每个控制器被配置为控制ACCRE中的一个，使得当输入偏移电压信号高于整流电压信号时，耦合到输出节点的ACCRE允许电流流过它，而另一个ACCRE被配置为允许电流流过它当输入失调电压信号低于整流电压信号时。

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