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11. 发明授权

US07230297B2 Trench-gated MOSFET including schottky diode therein 有权
标题翻译：沟槽栅MOSFET，其中包括肖特基二极管
公开(公告)号：US07230297B2
公开(公告)日：2007-06-12
申请号：US11127224
申请日：2005-05-12
申请人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/1095
摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
摘要翻译：公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。

12. 发明授权

US07227225B2 Semiconductor device having a vertical MOS trench gate structure 失效
标题翻译：具有垂直MOS沟槽栅极结构的半导体器件
公开(公告)号：US07227225B2
公开(公告)日：2007-06-05
申请号：US10829173
申请日：2004-04-22
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933
摘要： A second semiconductor region is formed on a first semiconductor region. A third semiconductor region is formed on a part of the second semiconductor region. A trench ranges from a surface of the third semiconductor region to the third semiconductor region and the second semiconductor region. The trench penetrates the third semiconductor region, and the depth of the trench is shorter than that of a deepest bottom portion of the second semiconductor region, and the second semiconductor region does not exist under a bottom surface of the trench. A gate insulating film is formed on facing side surfaces of the trench. First and second gate electrodes are formed on the gate insulating film. The first and second gate electrodes are separated from each other. The conductive material is formed between the first and second gate electrodes on the side surfaces of the trench, with an insulating film intervened therebetween.
摘要翻译：在第一半导体区域上形成第二半导体区域。在第二半导体区域的一部分上形成第三半导体区域。沟槽的范围从第三半导体区域的表面到第三半导体区域和第二半导体区域。沟槽穿透第三半导体区域，并且沟槽的深度比第二半导体区域的最深底部的深度短，并且第二半导体区域不存在于沟槽的底表面之下。栅极绝缘膜形成在沟槽的相对的侧表面上。在栅极绝缘膜上形成第一和第二栅电极。第一和第二栅电极彼此分离。导电材料形成在沟槽的侧表面上的第一和第二栅电极之间，绝缘膜介于其间。

13. 发明申请

US20070194372A1 TRENCH-GATED MOSFET INCLUDING SCHOTTKY DIODE THEREIN 有权
标题翻译：包含肖特基二极管的TRENCH-GFET MOSFET
公开(公告)号：US20070194372A1
公开(公告)日：2007-08-23
申请号：US11740045
申请日：2007-04-25
申请人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L31/00
CPC分类号： H01L29/7813 , H01L29/1095
摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
摘要翻译：公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。

14. 发明申请

US20050258479A1 Trench MOSFET 有权
标题翻译：沟槽MOSFET
公开(公告)号：US20050258479A1
公开(公告)日：2005-11-24
申请号：US11127224
申请日：2005-05-12
申请人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/423 , H01L21/336 , H01L21/8234 , H01L27/06 , H01L29/10 , H01L29/41 , H01L29/47 , H01L29/49 , H01L29/78 , H01L29/872 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/1095
摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
摘要翻译：公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。

15. 发明申请

US20050001264A1 Semiconductor device having verical MOS gate structure and method of manufacturing the same 失效
标题翻译：具有真正的MOS栅极结构的半导体器件及其制造方法
公开(公告)号：US20050001264A1
公开(公告)日：2005-01-06
申请号：US10829173
申请日：2004-04-22
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L29/78 , H01L21/3205 , H01L21/336 , H01L29/08 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/76
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933
摘要： A second semiconductor region is formed on a first semiconductor region. A third semiconductor region is formed on a part of the second semiconductor region. A trench ranges from a surface of the third semiconductor region to the third semiconductor region and the second semiconductor region. The trench penetrates the third semiconductor region, and the depth of the trench is shorter than that of a deepest bottom portion of the second semiconductor region, and the second semiconductor region does not exist under a bottom surface of the trench. A gate insulating film is formed on facing side surfaces of the trench. First and second gate electrodes are formed on the gate insulating film. The first and second gate electrodes are separated from each other. The conductive material is formed between the first and second gate electrodes on the side surfaces of the trench, with an insulating film intervened therebetween.
摘要翻译：在第一半导体区域上形成第二半导体区域。在第二半导体区域的一部分上形成第三半导体区域。沟槽的范围从第三半导体区域的表面到第三半导体区域和第二半导体区域。沟槽穿透第三半导体区域，并且沟槽的深度比第二半导体区域的最深底部的深度短，并且第二半导体区域不存在于沟槽的底表面之下。栅极绝缘膜形成在沟槽的相对的侧表面上。在栅极绝缘膜上形成第一和第二栅电极。第一和第二栅电极彼此分离。导电材料形成在沟槽的侧表面上的第一和第二栅电极之间，绝缘膜介于其间。

16. 发明授权

US07564097B2 Trench-gated MOSFET including schottky diode therein 有权
标题翻译：沟槽栅MOSFET，其中包括肖特基二极管
公开(公告)号：US07564097B2
公开(公告)日：2009-07-21
申请号：US11740045
申请日：2007-04-25
申请人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/1095
摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
摘要翻译：公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。

17. 发明申请

US20050287744A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050287744A1
公开(公告)日：2005-12-29
申请号：US11157908
申请日：2005-06-22
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L21/336 , H01L29/06 , H01L29/76 , H01L29/78 , H01L29/872 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/7806 , H01L29/872
摘要： A semiconductor device has a plurality of pillars formed by filling a poly-silicon via an insulating layer in a plurality of trenches arranged substantially in parallel at certain intervals, n+-semiconductor regions and p+-semiconductor regions which are formed between partial pillars among the plurality of pillars and alternately formed along a direction where the pillars extend, n−-semiconductor regions arranged between the other partial neighboring pillars among the plurality of pillars and a first metal layer which makes a schottky contact on an upper face of the n−-semiconductor regions.
摘要翻译：半导体器件具有通过多个沟槽中的绝缘层填充多晶硅形成的多个柱，所述多个沟槽基本上以一定间隔平行设置，n + + - 半导体区域和p + 在多个柱之间的部分柱之间形成并且沿着柱延伸的方向交替形成的半导体区域，其间布置在其中的相邻部分相邻柱之间的半导体区域多个柱状物以及在第n个半导体区域的上表面上形成肖特基接触的第一金属层。

18. 发明申请

US20050029586A1 Semiconductor device having trench gate structure and manufacturing method thereof 有权
标题翻译：具有沟槽栅极结构的半导体器件及其制造方法
公开(公告)号：US20050029586A1
公开(公告)日：2005-02-10
申请号：US10682111
申请日：2003-10-10
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L21/336 , H01L29/08 , H01L29/267 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/267 , H01L29/42368 , H01L29/4933
摘要： A vertical MOSFET includes a base region formed on a drain region and a source region formed in the base region. A trench is formed to extend from the surface of the source region and penetrate the source region and has depth to reach a portion near the drain region. A gate insulating film is formed on the side walls and bottom portion of the trench and the gate electrode is formed in the trench. The impurity concentration profile of the base region has a first peak in a portion near the interface between the source region and the base region and a second peak which is formed in a portion near the interface between the base region and the drain region and is lower than the first peak. The threshold voltage is determined based on the first peak and the dose amount is determined based on the second peak.
摘要翻译：垂直MOSFET包括形成在漏极区域上的基极区域和形成在基极区域中的源极区域。沟槽形成为从源极区域的表面延伸并且穿透源极区域并且具有深度以到达漏极区域附近的部分。在沟槽的侧壁和底部形成栅极绝缘膜，并且在沟槽中形成栅电极。基极区域的杂质浓度分布在源极区域和基极区域之间的界面附近的部分具有第一峰值，第二峰值形成在基极区域和漏极区域之间的界面附近的部分，并且较低比第一个高峰。基于第一峰确定阈值电压，并且基于第二峰确定剂量。

19. 发明授权

US06838730B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06838730B1
公开(公告)日：2005-01-04
申请号：US10781688
申请日：2004-02-20
申请人： Yusuke Kawaguchi , Syotaro Ono , Yoshihiro Yamaguchi , Akio Nakagawa
发明人： Yusuke Kawaguchi , Syotaro Ono , Yoshihiro Yamaguchi , Akio Nakagawa
IPC分类号： H01L29/06 , H01L29/08 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0847 , H01L29/4236 , H01L29/4238
摘要： A semiconductor device comprises a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type formed in an upper surface of the first semiconductor layer, resistance of the second semiconductor layer being higher than that of the first semiconductor layer, a base layer of a second conductivity type formed on the second semiconductor layer, gate electrodes deposited in a plurality of first trenches, a gate insulation film being disposed between inner walls and the gate electrodes, each of the first trenches having a band-shaped planar pattern and extending from top of the base layer down to the upper surface of the second semiconductor layer, bridge electrodes filling a plurality of second trenches and surrounded by an insulation film deposited over walls of the trenches, the second trenches extending from the top of the base layer down to the upper surface of the second semiconductor layer and connecting adjacent ones of the first trenches in communication with one another so that each of the bridge electrodes electrically connects adjacent ones of the gate electrodes, an impurity diffused region of the second conductivity type formed in the second semiconductor layer adapted to surround the second trenches existing in the second semiconductor layer, a source region of the first conductivity type formed in a surface area of the base layer alongside extensions of the gate electrodes, a source electrode formed on the surface of the source region, and a drain electrode formed on a back surface of the first semiconductor layer.
摘要翻译：半导体器件包括第一导电类型的第一半导体层，形成在第一半导体层的上表面中的第一导电类型的第二半导体层，第二半导体层的电阻高于第一半导体层的电阻，形成在第二半导体层上的第二导电类型的基极层，沉积在多个第一沟槽中的栅电极，栅极绝缘膜设置在内壁和栅电极之间，每个第一沟槽具有带状平面图案并从基底层的顶部向下延伸到第二半导体层的上表面，桥接电极填充多个第二沟槽并由沉积在沟槽的壁上的绝缘膜围绕，第二沟槽从第二沟槽的顶部延伸基底层向下延伸到第二半导体层的上表面并且连接相邻的第一熔丝 t沟槽彼此连通，使得每个桥电极电连接相邻的栅极电极，形成在第二半导体层中的适于包围存在于第二半导体层中的第二沟槽的第二导电类型的杂质扩散区域形成在基极层的表面区域的栅极电极的延伸部分上形成的第一导电类型的源极区域，形成在源极区域的表面上的源极电极和形成在第一半导体的背面上的漏极电极层。

20. 发明授权

US06818945B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06818945B2
公开(公告)日：2004-11-16
申请号：US10404141
申请日：2003-04-02
申请人： Yusuke Kawaguchi , Syotaro Ono , Akio Nakagawa
发明人： Yusuke Kawaguchi , Syotaro Ono , Akio Nakagawa
IPC分类号： H01L2972
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/41741
摘要： A semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate of a first conductive type; a semiconductor layer of the first conductive type formed on the semiconductor substrate; a base layer of a second conductive type formed on the semiconductor layer; a plurality of columns of stripe trenches formed at predetermined intervals from a surface of the base layer by a predetermined depth; insulating films formed on side surfaces and bottoms of the trenches, respectively; source layers of the first conductive type formed on surface layer portions of the base layer between the trenches, respectively; stripe contact layers of the second conductive type formed each at centers of the surface layer portions of the base layer between the trenches, respectively; a gate electrode formed in every other trench among the plurality of columns of trenches; source electrodes formed in the trenches other than the trenches in which the gate electrodes are formed and on the source layers and the contact layers, respectively; and a drain electrode formed on a rear surface of the semiconductor substrate.
摘要翻译：根据本发明的一个实施例的半导体器件包括：第一导电类型的半导体衬底; 形成在所述半导体衬底上的所述第一导电类型的半导体层; 形成在所述半导体层上的第二导电类型的基底层; 多个柱状的条形槽，以预定的距离从基底层的表面形成预定的深度; 分别形成在沟槽的侧表面和底部的绝缘膜; 分别形成在沟槽之间的基底层的表层部分上的第一导电类型的源极层; 分别在沟槽之间的基底层的表层部分的中心分别形成第二导电类型的条状接触层; 形成在所述多个沟槽列之间的每隔一个沟槽中的栅电极; 源极电极分别形成在不同于其中形成栅电极的沟槽之外的沟槽中，并分别在源极层和接触层上形成; 以及形成在所述半导体衬底的后表面上的漏电极。

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