专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5352913A Dynamic memory storage capacitor having reduced gated diode leakage 失效
标题翻译：具有降低的门控二极管泄漏的动态存储器存储电容器
公开(公告)号：US5352913A
公开(公告)日：1994-10-04
申请号：US204909
申请日：1994-03-02
申请人： Gishi Chung , William R. McKee , Clarence W. Teng
发明人： Gishi Chung , William R. McKee , Clarence W. Teng
IPC分类号： H01L27/10 , H01L21/02 , H01L21/8242 , H01L27/108 , H01L29/68 , H01L29/92
CPC分类号： H01L27/10861 , H01L28/40
摘要： A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. Trenches are etched into a face of a body of semiconductor material. Storage nodes surrounding the trenches are created. A polysilicon layer is formed on the trench walls. A storage dielectric layer is formed on the trench walls, adjacent to the layer of polysilicon on the trench walls, so that the layer of polysilicon on the trench walls lies between the storage dielectric layer and the storage node. The layer of polysilicon on the trench walls reduces leakage current from the storage node. A trench type field plate isolated random access memory cell structure is also disclosed.
摘要翻译：公开了一种在沟槽电容器型场板隔离型动态随机存取存储器件中降低栅极二极管泄漏的方法。沟槽蚀刻成半导体材料体的表面。创建围绕沟槽的存储节点。在沟槽壁上形成多晶硅层。在与沟槽壁上的多晶硅层相邻的沟槽壁上形成存储电介质层，使得沟槽壁上的多晶硅层位于存储介电层和存储节点之间。沟槽壁上的多晶硅层减少了来自存储节点的泄漏电流。还公开了沟槽型场板隔离随机存取存储单元结构。

12. 发明授权

US5252506A Method to eliminate gate filaments on field plate isolated devices 失效
标题翻译：在场板隔离装置上消除栅极细丝的方法
公开(公告)号：US5252506A
公开(公告)日：1993-10-12
申请号：US879697
申请日：1992-05-05
申请人： Duane E. Carter , William R. McKee , Gishi Chung , Fred D. Fishburn
发明人： Duane E. Carter , William R. McKee , Gishi Chung , Fred D. Fishburn
IPC分类号： H01L21/8242 , H01L21/306
CPC分类号： H01L27/10861
摘要： A method is disclosed for preventing formation of undesirable polysilicon word line gate filaments in integrated circuit devices such as VLSI dynamic random access memories employing field plate isolation. Before the word lines are processed, an oxide layer is formed in the field plate openings beneath sidewalls of nitride along the edges of the field plate openings. The oxide layer partially fills an undercut area beneath a dip out of the sidewall of nitride. The dip out of the sidewall of nitride is removed. The removal of the dip out and the partial filling of the undercut area reduces the possibility of polysilicon word line filaments from forming around the edge of the field plate openings in the undercut area when the word lines are later added. A field plate isolated memory device is also disclosed wherein along the edges of the field plate openings, the partially filling oxide layer and the sidewall nitride layer are approximately coincident.
摘要翻译：公开了一种用于防止在诸如使用场板隔离的VLSI动态随机存取存储器的集成电路器件中形成不需要的多晶硅字线栅极细丝的方法。在处理字线之前，沿着场板开口的边缘在氮化物侧壁下方的场板开口中形成氧化物层。氧化物层部分地填充氮化物侧壁下方的浸渍下方的底切区域。去除氮化物侧壁的浸出。脱落区域的去除以及部分填充底切区域减少了当字线稍后添加时，多晶硅字线细丝在底切区域的场板开口的边缘周围形成的可能性。还公开了一种场板隔离存储器件，其中沿着场板开口的边缘，部分填充的氧化物层和侧壁氮化物层几乎重合。

13. 发明申请

US20060000704A1 Solution treatment apparatus and solution treatment method 审中-公开
标题翻译：溶液处理装置和溶液处理方法
公开(公告)号：US20060000704A1
公开(公告)日：2006-01-05
申请号：US10530678
申请日：2003-06-04
申请人： Hiroshi Sato , Gishi Chung
发明人： Hiroshi Sato , Gishi Chung
IPC分类号： C23C14/00
CPC分类号： C25D17/008 , C25D17/001
摘要： A solution treatment apparatus of the present invention includes a diaphragm position varying mechanism configured to partly vary the position of a diaphragm. According to the solution treatment apparatus of the present invention, partial positional change of the diaphragm is possible. Therefore, uniformity of solution treatment in a surface of a substrate can be effectively improved.
摘要翻译：本发明的固溶处理装置包括：隔膜位置变化机构，被配置为部分地改变隔膜的位置。根据本发明的固溶处理装置，隔膜的部分位置变化是可能的。因此，能够有效地提高基板表面的固溶处理的均匀性。

14. 发明授权

US5112762A High angle implant around top of trench to reduce gated diode leakage 失效
标题翻译：在沟槽顶部的高角度植入物，以减少栅极二极管泄漏
公开(公告)号：US5112762A
公开(公告)日：1992-05-12
申请号：US622468
申请日：1990-12-05
申请人： Dirk N. Anderson , William R. McKee , Gishi Chung
发明人： Dirk N. Anderson , William R. McKee , Gishi Chung
IPC分类号： H01L21/265 , H01L21/316 , H01L21/32 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L29/66181 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/26586 , H01L21/31662 , H01L21/32
摘要： A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. The storage node of the capacitor is formed by placing a storage node material, such as implanted arsenic, into the trench walls of the device at a first tilt and a second tilt. The angle of the second tilt is preferably larger, higher, than the angle of the first tilt. This higher angle provides the storage node with a larger concentration of doping around the upper portion the trench walls. This larger concentration of doping reduces the charge leaking from the upper portion of the storage node into the substrate of semiconductor material. A trench type storage capacitor for a dynamic random access memory device is also disclosed.
摘要翻译：公开了一种在沟槽电容器型场板隔离型动态随机存取存储器件中降低栅极二极管泄漏的方法。电容器的存储节点通过将诸如注入的砷的存储节点材料以第一倾斜和第二倾斜放置在器件的沟槽壁中而形成。第二倾斜的角度优选地比第一倾斜的角度更大，更高。这种较高的角度为存储节点提供了围绕沟槽壁上部的更大的掺杂浓度。这种较大的掺杂浓度降低了从存储节点的上部泄漏到半导体材料的衬底中的电荷。还公开了一种用于动态随机存取存储器件的沟槽型存储电容器。

15. 发明申请

US20090085130A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090085130A1
公开(公告)日：2009-04-02
申请号：US10585828
申请日：2005-01-28
申请人： Kenji Suzuki , Gishi Chung , Kazuya Okubo
发明人： Kenji Suzuki , Gishi Chung , Kazuya Okubo
IPC分类号： H01L29/78
CPC分类号： C23C16/30 , C23C16/42 , H01L21/28088 , H01L29/4966
摘要： The present invention relates to a semiconductor device comprising a semiconductor substrate (1), a gate insulator formed on this substrate, such as a gate oxide film (2), and a gate electrode (3) formed on the insulator. The gate electrode (3) has a metallic compound film (3a). This metallic compound film (3a) is formed by CVD using a material containing a metal carbonyl, e.g., W(CO)6 gas, and at least one of a Si-containing gas and a N-containing gas. The work function of the metallic compound film (3a) thus formed is controllable by the Si and/or N content of the film.
摘要翻译：本发明涉及一种半导体器件，包括半导体衬底（1），形成在该衬底上的栅极绝缘体（例如栅极氧化膜）和形成在绝缘体上的栅电极。栅电极（3）具有金属化合物膜（3a）。该金属化合物膜（3a）通过CVD使用含有羰基金属如W（CO）6气体的材料和含Si气体和含N气体中的至少一种来形成。由此形成的金属化合物膜（3a）的功函数可以通过膜的Si和/或N含量来控制。

16. 发明授权

US06949829B2 Semiconductor device and fabrication method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US06949829B2
公开(公告)日：2005-09-27
申请号：US10380038
申请日：2001-09-11
申请人： Takashi Akahori , Gishi Chung , Kohei Kawamura
发明人： Takashi Akahori , Gishi Chung , Kohei Kawamura
IPC分类号： H01L21/314 , H01L21/768 , H01L23/532 , H01L23/48 , H01L21/4763
CPC分类号： H01L21/76807 , H01L21/314 , H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： With a stopper layer 19 as an etching stopper, a second groove 14a and a contact hole 13a are formed. Copper is buried inside the second groove 14a and the contact hole 13a, thereby forming a plug layer 22 and an overlying wiring layer 21 connected to an underlying wiring layer 17 via the plug layer 22. The stopper layer 19 is comprised of Si, C and N as essential components. First and second cap layers 18 and 23 are also comprised of Si, C and N as essential components.
摘要翻译：作为蚀刻停止件的阻挡层19形成有第二槽14a和接触孔13a。铜被埋在第二槽14a和接触孔13a内，由此形成插头层22和覆盖的布线层21，该布线层21经由插塞层22连接到下面的布线层17。阻挡层19由Si，C和N组成。第一和第二盖层18和23也由Si，C和N组成。

17. 发明申请

US20050170093A1 Coating device and coating method 审中-公开
标题翻译：涂布装置和涂布方法
公开(公告)号：US20050170093A1
公开(公告)日：2005-08-04
申请号：US10502797
申请日：2003-02-03
申请人： Gishi Chung , Michio Tanaka
发明人： Gishi Chung , Michio Tanaka
IPC分类号： G03F7/16 , B05C5/02 , B05C9/14 , B05C11/00 , B05D1/26 , B05D5/12 , B05D7/00 , H01L21/00 , H01L21/027 , H01L21/288 , H01L21/768 , B05D5/00
CPC分类号： H01L21/6715 , H01L21/288 , H01L21/76819 , H01L21/7684
摘要： A coating apparatus (10) includes: a substrate holding section (16) which holds a substrate having a step on a major surface; a coating section (31) which applies a plurality of liquids different in viscosity from each other on a substrate; and a control section (70) which controls the coating section according to an arrangement of a step on the substrate. It is possible to effectively eliminate the steps of the substrate by applying the plural liquids different in viscosity according to the arrangement of the steps.
摘要翻译：涂覆装置（10）包括：基板保持部（16），其保持具有在主表面上的台阶的基板; 涂布部分，其在基板上施加彼此不同粘度的多种液体; 以及控制部（70），其根据所述基板上的台阶的配置来控制所述涂布部。根据步骤的布置，可以通过施加不同粘度的多种液体来有效地消除基板的步骤。

18. 发明授权

US5251168A Boundary cells for improving retention time in memory devices 失效
标题翻译：边界细胞，用于改善记忆装置的保留时间
公开(公告)号：US5251168A
公开(公告)日：1993-10-05
申请号：US738383
申请日：1991-07-31
申请人： Gishi Chung , William R. McKee , William F. Richardson , Lionel S. White, Jr.
发明人： Gishi Chung , William R. McKee , William F. Richardson , Lionel S. White, Jr.
IPC分类号： H01L23/495 , H01L27/105 , H01L27/108 , G11C7/02
CPC分类号： H01L23/4951 , H01L27/10805 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L24/48 , H01L27/105 , H01L2924/00014 , H01L2924/01014 , H01L2924/10253 , H01L2924/14 , H01L2924/19041
摘要： By placing boundary cells within areas of discontinuity of a memory array, such as in word line strap areas, stress on edge cells of the memory array is reduced; the reduction of stress improves leakage characteristics and pause-refresh capabilities of edge cells. The boundary cells may further be laid out in the areas of discontinuity with the same pattern as the memory array. Some of the boundary cells may be electrically biased to act as minority carrier sinks. By collecting minority carriers that otherwise may be attracted to edge cells of the memory array, the leakage characteristics of the edge cells and their pause-refresh capabilities are further enhanced. The boundary cells are particularly useful in improving leakage characteristics of dynamic random access memory devices of the trench capacitor type.
摘要翻译：通过将边界单元放置在存储器阵列的不连续区域内，例如在字线带区域中，存储器阵列的边缘单元上的应力减小; 压力的降低提高了边缘电池的泄漏特性和暂停刷新能力。边界单元可以进一步布置在具有与存储器阵列相同的图案的不连续区域中。一些边界单元可以被电偏置以用作少数载流子阱。通过收集否则可能被吸引到存储器阵列的边缘单元的少数载流子，边缘单元的泄漏特性及其暂停刷新能力得到进一步提高。边界电池特别适用于改善沟槽电容器型动态随机存取存储器件的泄漏特性。

19. 发明授权

US5202279A Poly sidewall process to reduce gated diode leakage 失效
标题翻译：聚侧壁工艺减少栅极二极管漏电
公开(公告)号：US5202279A
公开(公告)日：1993-04-13
申请号：US622465
申请日：1990-12-05
申请人： Gishi Chung , William R. McKee , Clarence W. Teng
发明人： Gishi Chung , William R. McKee , Clarence W. Teng
IPC分类号： H01L27/10 , H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L28/40
摘要： A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. Trenches are etched into a face of a body of semiconductor material. Storage nodes surrounding the trenches are created. A polysilicon layer is formed on the trench walls. A storage dielectric layer is formed on the trench walls, adjacent to the layer of polysilicon on the trench walls, so that the layer of polysilicon on the trench walls lies between the storage dielectric layer and the storage node. The layer of polysilicon on the trench walls reduces leakage current from the storage node. A trench type field plate isolated random access memory cell structure is also disclosed.
摘要翻译：公开了一种在沟槽电容器型场板隔离型动态随机存取存储器件中降低栅极二极管泄漏的方法。沟槽蚀刻成半导体材料体的表面。创建围绕沟槽的存储节点。在沟槽壁上形成多晶硅层。在与沟槽壁上的多晶硅层相邻的沟槽壁上形成存储电介质层，使得沟槽壁上的多晶硅层位于存储介电层和存储节点之间。沟槽壁上的多晶硅层减少了来自存储节点的泄漏电流。还公开了沟槽型场板隔离随机存取存储单元结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式