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11. 发明申请

US20080288691A1 METHOD AND APPARATUS OF LOCK TRANSACTIONS PROCESSING IN SINGLE OR MULTI-CORE PROCESSOR 审中-公开
标题翻译：单个或多个核心处理器的锁定交易处理方法与装置
公开(公告)号：US20080288691A1
公开(公告)日：2008-11-20
申请号：US12115643
申请日：2008-05-06
申请人： Xiao Yuan Bie , Yi Ge , Zhiyong Liang , Peng Shao , Wen Bo Shen
发明人： Xiao Yuan Bie , Yi Ge , Zhiyong Liang , Peng Shao , Wen Bo Shen
IPC分类号： G06F12/14
CPC分类号： G06F9/526 , G06F2209/521 , G06F2209/522
摘要： The present invention relates to a method and apparatus of lock transactions processing in a single or multi-core processor. An embodiment of the present invention is a processor with one or more processing cores, an address arbitrator, where one or more processing cores are configured to submit a lock transaction request to the address arbitrator corresponding to a specific instruction in response to the execution of the specific instruction. The lock transaction request includes a lock variable address asserted on an address bus. The processor further includes a lock controller for performing lock transaction processing in response to the lock transaction request, and notifying processing result to the processing core from which the lock transaction request was sent. The processor further includes a switching device, coupled to the address arbitrator and the lock controller, for identifying the lock transaction request and notifying the lock transaction request to the lock controller.
摘要翻译：本发明涉及一种在单核或多核处理器中锁交易处理的方法和装置。本发明的实施例是具有一个或多个处理核心的处理器，地址仲裁器，其中一个或多个处理核心被配置为响应于执行该特定指令而向与地址仲裁器相对应的特定指令提交锁交易请求具体说明。锁交易请求包括在地址总线上断言的锁定变量地址。该处理器还包括一个锁定控制器，用于响应锁定事务请求执行锁定事务处理，并将处理结果通知处理核心，锁定事务请求被发送到该处理核心。处理器还包括耦合到地址仲裁器和锁定控制器的交换设备，用于识别锁交易请求并通知锁定控制器的锁定事务请求。

12. 发明授权

US07953915B2 Interrupt dispatching method in multi-core environment and multi-core processor 失效
标题翻译：多核环境和多核处理器中的中断调度方式
公开(公告)号：US07953915B2
公开(公告)日：2011-05-31
申请号：US12412286
申请日：2009-03-26
申请人： Yi Ge , ChaoJun Liu , Wen Bo Shen , Yuan Ping
发明人： Yi Ge , ChaoJun Liu , Wen Bo Shen , Yuan Ping
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F9/505
摘要： Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are divided into a plurality of groups of cores, where N is a positive integer greater than one. The method generates a token in response to an arriving interrupt; determines a group of cores to be preferentially used to handle the interrupt as a hot group in accordance with the interrupt; and sends the token to the hot group, determines sequentially from the first core in the hot group whether an interrupt dispatch termination condition is satisfied, and determines the current core as a response core to be used to handle the interrupt upon determining satisfaction of the interrupt dispatch termination condition. With the invention, delay in responding to an interrupt by the processor is reduced providing optimized performance of the processor.
摘要翻译：公开了一种多核处理器环境中的中断调度系统和方法。该处理器包括中断调度器和能够进行中断处理的N个核，其被分成多组核心，其中N是大于1的正整数。该方法响应于到达中断产生令牌; 根据中断，确定要优先用于处理中断的一组核心作为热组; 并将令牌发送到热组，从热组中的第一核心顺序地确定是否满足中断分派终止条件，并且在确定中断满足时将当前核心确定为用于处理中断的响应核心调度终止条件。利用本发明，减少了处理器对中断的响应延迟，从而提供了处理器的优化性能。

13. 发明申请

US20090248984A1 METHOD AND DEVICE FOR PERFORMING COPY-ON-WRITE IN A PROCESSOR 审中-公开
标题翻译：用于在处理器中执行复写的方法和设备
公开(公告)号：US20090248984A1
公开(公告)日：2009-10-01
申请号：US12410325
申请日：2009-03-24
申请人： Xiao Wei Shen , Hua Yong Wang , Wen Bo Shen , Peng Shao
发明人： Xiao Wei Shen , Hua Yong Wang , Wen Bo Shen , Peng Shao
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0884 , G06F12/0811
摘要： There are disclosed a method and device for performing Copy-on-Write in a processor. The processor comprises: processor cores, L1 caches each of which is logically divided into a first L1 cache and a second L1 cache, and L2 caches. The first L1 cache is used for saving new data value, and the second L1 cache for saving old data value. The method can comprise the steps of: in response to a store operation from said processor core, judging whether a corresponding cache line in said L2 cache has been modified; if it is determined a corresponding L2 cache line in said L2 cache has not been modified, copying old data value in the corresponding L2 cache line to said second L1 cache, and writing new data value to the corresponding L2 cache line; and if it is determined a corresponding L2 cache line in said L2 cache has been modified, writing new data value to the corresponding L2 cache line directly.
摘要翻译：公开了一种用于在处理器中执行写时复制的方法和装置。处理器包括：处理器核心，L1高速缓存，其中每个高速缓存被逻辑地划分为第一L1高速缓存和第二L1高速缓存以及L2高速缓存。第一个L1缓存用于保存新数据值，第二个L1缓存用于保存旧数据值。该方法可以包括以下步骤：响应于来自所述处理器核心的存储操作，判断所述L2高速缓存中的相应高速缓存行是否已被修改; 如果确定所述L2高速缓存中的对应的L2高速缓存行尚未被修改，则将相应的L2高速缓存行中的旧数据值复制到所述第二L1高速缓存，并将新的数据值写入对应的L2高速缓存行; 并且如果确定了所述L2高速缓存中的对应的L2高速缓存行已被修改，则将新的数据值直接写入对应的L2高速缓存行。

14. 发明申请

US20090248934A1 INTERRUPT DISPATCHING METHOD IN MULTI-CORE ENVIRONMENT AND MULTI-CORE PROCESSOR 失效
标题翻译：多核环境和多核处理器的中断分配方法
公开(公告)号：US20090248934A1
公开(公告)日：2009-10-01
申请号：US12412286
申请日：2009-03-26
申请人： Yi Ge , ChaoJun Liu , Wen Bo Shen , Yuan Ping
发明人： Yi Ge , ChaoJun Liu , Wen Bo Shen , Yuan Ping
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F9/505
摘要： Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are divided into a plurality of groups of cores, where N is a positive integer greater than one. The method generates a token in response to an arriving interrupt; determines a group of cores to be preferentially used to handle the interrupt as a hot group in accordance with the interrupt; and sends the token to the hot group, determines sequentially from the first core in the hot group whether an interrupt dispatch termination condition is satisfied, and determines the current core as a response core to be used to handle the interrupt upon determining satisfaction of the interrupt dispatch termination condition. With the invention, delay in responding to an interrupt by the processor is reduced providing optimized performance of the processor.
摘要翻译：公开了一种多核处理器环境中的中断调度系统和方法。该处理器包括中断调度器和能够进行中断处理的N个核，其被分成多组核心，其中N是大于1的正整数。该方法响应于到达中断产生令牌; 根据中断，确定要优先用于处理中断的一组核心作为热组; 并将令牌发送到热组，从热组中的第一核心顺序地确定是否满足中断分派终止条件，并且在确定中断满足时将当前核心确定为用于处理中断的响应核心调度终止条件。利用本发明，减少了处理器对中断的响应延迟，从而提供了处理器的优化性能。

15. 发明授权

US08418047B2 Data bus system, its encoder/decoder and encoding/decoding method 有权
标题翻译：数据总线系统，其编码器/解码器和编码/解码方式
公开(公告)号：US08418047B2
公开(公告)日：2013-04-09
申请号：US13446565
申请日：2012-04-13
申请人： Wen Bo Shen , Chao-Jun Liu , Yi Gee , Qiang Liu
发明人： Wen Bo Shen , Chao-Jun Liu , Yi Gee , Qiang Liu
IPC分类号： H04L1/00
CPC分类号： G06F11/10
摘要： The present application relates to a data bus system, its encoder/decoder and encoding/decoding method. The data bus encoder comprises: a bus-invert encoder for generating encoded data and invert-indication information by performing bus-invert encoding on data according to a predetermined bus-invert encoding scheme; a virtual bit-group generator for converting the invert-indication information into a virtual bit-group according to a predetermined code mapping; and an error-checking-and-correction encoder for generating an error-checking-and-correction code for a virtual word according to a predetermined error-checking-and-correction encoding scheme, wherein the number of error-checking bits is more than the number of error-correction bits at least by one in the predetermined error-checking-and-correction encoding scheme, and the virtual word includes the data to be output, the virtual bit-group corresponding to the data, and at least one padding bit of a fixed value, which is configured as required by the error-checking-and-correction encoding scheme.
摘要翻译：本申请涉及数据总线系统，其编码器/解码器和编码/解码方法。数据总线编码器包括：总线反转编码器，用于通过根据预定的总线反转编码方案对数据执行总线反转编码来产生编码数据和反转指示信息; 虚拟位组生成器，用于根据预定的代码映射将反转指示信息转换为虚拟位组; 以及用于根据预定的错误检查和校正编码方案为虚拟字生成错误校验码的纠错编码器，其中错误校验位的数目大于在预定的错误校验和校正编码方案中至少一个纠错位的数量，虚拟字包括要输出的数据，对应于数据的虚拟位组，以及至少一个填充位，其被配置为由错误校验和校正编码方案所要求的。

16. 发明授权

US08181101B2 Data bus system, its encoder/decoder and encoding/decoding method 有权
标题翻译：数据总线系统，其编码器/解码器和编码/解码方法
公开(公告)号：US08181101B2
公开(公告)日：2012-05-15
申请号：US12363128
申请日：2009-01-30
申请人： Wen Bo Shen , Chao-Jun Liu , Yi Ge , Qiang Liu
发明人： Wen Bo Shen , Chao-Jun Liu , Yi Ge , Qiang Liu
IPC分类号： H03L1/00
CPC分类号： G06F11/10
摘要： The present application relates to a data bus system, its encoder/decoder and encoding/decoding method. The data bus encoder comprises: a bus-invert encoder for generating encoded data and invert-indication information by performing bus-invert encoding on data according to a predetermined bus-invert encoding scheme; a virtual bit-group generator for converting the invert-indication information into a virtual bit-group according to a predetermined code mapping; and an error-checking-and-correction encoder for generating an error-checking-and-correction code for a virtual word according to a predetermined error-checking-and-correction encoding scheme, wherein the number of error-checking bits is more than the number of error-correction bits at least by one in the predetermined error-checking-and-correction encoding scheme, the mapping is such that the Hamming distance between any possible value of the virtual bit-group and a reference virtual bit-group which cannot be converted into under the mapping is a fixed value, and not greater than the number of error-correction bits of the error-checking-and-correction encoding scheme, and the virtual word includes the data to be output, the virtual bit-group corresponding to the data, and at least one padding bit of a fixed value, which is configured as required by the error-checking-and-correction encoding scheme.
摘要翻译：本申请涉及数据总线系统，其编码器/解码器和编码/解码方法。数据总线编码器包括：总线反转编码器，用于通过根据预定的总线反转编码方案对数据执行总线反转编码来产生编码数据和反转指示信息; 虚拟位组生成器，用于根据预定的代码映射将反转指示信息转换为虚拟位组; 以及用于根据预定的错误检查和校正编码方案为虚拟字生成错误校验码的纠错编码器，其中错误校验位的数目大于在预定的错误校验和校正编码方案中至少一个纠错位的数量，映射使得虚拟位组的任何可能值和参考虚拟位组之间的汉明距离，其中不能转换成映射为固定值，并且不大于错误校验和校正编码方案的纠错位数，虚拟字包括要输出的数据，虚拟位 - 对应于数据的组，以及被配置为由错误校验和校正编码方案所要求的固定值的至少一个填充位。

17. 发明申请

US20090193319A1 DATA BUS SYSTEM, ITS ENCODER/DECODER AND ENCODING/DECODING METHOD 有权
标题翻译：数据总线系统，其编码器/解码器和编码/解码方法
公开(公告)号：US20090193319A1
公开(公告)日：2009-07-30
申请号：US12363128
申请日：2009-01-30
申请人： Wen Bo Shen , Chao-Jun Liu , Yi Ge , Qiang Liu
发明人： Wen Bo Shen , Chao-Jun Liu , Yi Ge , Qiang Liu
IPC分类号： H03M13/13 , G06F11/10
CPC分类号： G06F11/10
摘要： The present application relates to a data bus system, its encoder/decoder and encoding/decoding method. The data bus encoder comprises: a bus-invert encoder for generating encoded data and invert-indication information by performing bus-invert encoding on data according to a predetermined bus-invert encoding scheme; a virtual bit-group generator for converting the invert-indication information into a virtual bit-group according to a predetermined code mapping; and an error-checking-and-correction encoder for generating an error-checking-and-correction code for a virtual word according to a predetermined error-checking-and-correction encoding scheme, wherein the number of error-checking bits is more than the number of error-correction bits at least by one in the predetermined error-checking-and-correction encoding scheme, the mapping is such that the Hamming distance between any possible value of the virtual bit-group and a reference virtual bit-group which cannot be converted into under the mapping is a fixed value, and not greater than the number of error-correction bits of the error-checking-and-correction encoding scheme, and the virtual word includes the data to be output, the virtual bit-group corresponding to the data, and at least one padding bit of a fixed value, which is configured as required by the error-checking-and-correction encoding scheme.
摘要翻译：本申请涉及数据总线系统，其编码器/解码器和编码/解码方法。数据总线编码器包括：总线反转编码器，用于通过根据预定的总线反转编码方案对数据执行总线反转编码来产生编码数据和反转指示信息; 虚拟位组生成器，用于根据预定的代码映射将反转指示信息转换为虚拟位组; 以及用于根据预定的错误检查和校正编码方案为虚拟字生成错误校验码的纠错编码器，其中错误校验位的数目大于在预定的错误校验和校正编码方案中至少一个纠错位的数量，映射使得虚拟位组的任何可能值和参考虚拟位组之间的汉明距离，其中不能转换成映射为固定值，并且不大于错误校验和校正编码方案的纠错位数，虚拟字包括要输出的数据，虚拟位 - 对应于数据的组，以及被配置为由错误校验和校正编码方案所要求的固定值的至少一个填充位。

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