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    • 19. 发明授权
    • Vector processor having a mask register used for performing nested
conditional instructions
    • 矢量处理器具有用于执行嵌套条件指令的掩码寄存器
    • US5604913A
    • 1997-02-18
    • US237305
    • 1994-05-03
    • Yoichi KoyanagiTakeshi Horie
    • Yoichi KoyanagiTakeshi Horie
    • G06F9/32G06F9/38G06F15/78G06F17/16G06F15/347
    • G06F17/16G06F15/8084G06F9/30036G06F9/30072G06F9/30094
    • In a computer equipped with a mask register in which is stored mask data indicating, for each array element, whether or not a statement such as an IF statement or an ELSE statement should be applied, the computer having a vector processor executing vector operation processing according to the mask data stored in the mask register, a first executing unit acquires first and second memory areas in which the mask data is saved in a stack formation. A second executing unit generates, when an IF statement appears in execution of a program, mask data indicating truth/falsity of a conditional expression of the IF statement, and saves the mask data indicating the truth/falsity of the conditional expression in the first memory area. A third executing unit reads latest mask data saved in the second memory area in synchronism with a process of the second executing unit. A fourth executing unit performs a bit-base logic operation on the mask data saved by the second executing unit and the mask data read by the third executing unit, stores mask data thus generated and applied to the IF statement in the mask register, and saves the above mask data applied to the above IF statement in the second memory area.
    • 在配备有掩码寄存器的计算机中,存储掩码数据,指示对于每个数组元素,是否应该应用诸如IF语句或ELSE语句的语句,具有向量处理器的计算机执行向量操作处理 对于存储在掩码寄存器中的掩码数据,第一执行单元获取在堆栈形成中保存掩码数据的第一和第二存储区域。 第二执行单元在执行程序时出现IF语句时,产生表示IF语句的条件表达式的真实/虚假的数据,并将表示条件表达式的真值/虚假的掩码数据保存在第一存储器中 区。 第三执行单元与第二执行单元的处理同步地读取保存在第二存储区域中的最新掩码数据。 第四执行单元对由第二执行单元保存的掩码数据和由第三执行单元读取的掩码数据执行位基逻辑运算,将由此生成并应用于掩码寄存器中的IF语句的掩码数据存储,并保存 上述掩码数据应用于第二存储区域中的上述IF语句。
    • 20. 发明授权
    • Synchronization control system in a parallel computer
    • 并行计算机中的同步控制系统
    • US5278975A
    • 1994-01-11
    • US715583
    • 1991-06-14
    • Hiroaki IshihataMorio IkesakaTakeshi Horie
    • Hiroaki IshihataMorio IkesakaTakeshi Horie
    • G06F9/46G06F15/80G06F1/04
    • G06F9/52G06F15/8007
    • An inter-processor synchronization control system in a distributed memory type parallel computer comprises a unit for detecting an establishment of the synchronization of all PEs, a status request register unit provided for each PE for independently issuing a status request through a status request signal, a unit for determining the issues of requests from status request registers of all PEs, a unit for distributing the determination to all PEs and a status detecting register for detecting the status according to the distributed determination and the output of the synchronization establishment detection unit. The inter-processor synchronous control system detects the status of all PEs when the synchronization is established in all PEs.
    • 分布式存储器型并行计算机中的处理器间同步控制系统包括用于检测所有PE的同步建立的单元,为每个PE提供的状态请求寄存器单元,用于通过状态请求信号独立地发出状态请求, 用于确定所有PE的状态请求寄存器的请求的问题的单元,用于向所有PE分配确定的单元和用于根据同步建立检测单元的分布式确定和输出来检测状态的状态检测寄存器。 当所有PE建立同步时,处理器间同步控制系统检测所有PE的状态。