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    • 11. 发明授权
    • Door closer having sound generating function
    • 具有声音发生功能的闭门器
    • US4763111A
    • 1988-08-09
    • US772803
    • 1985-09-05
    • Isamu MatsuoJunji Mori
    • Isamu MatsuoJunji Mori
    • G08B3/10G08B13/08H01H3/16
    • G08B13/08G08B3/10
    • A door closer which is capable of issuing a selected sound or remaining silent when the associated door is opened and which can be mounted on an existing door opener mechanism. Two covers are provided which are mounted on opposite ends of a door closer mechanism body. One of the two covers carries a speaker, while the other carries a sound generating circuit, sensors, and a changeover switch. The changeover switch is used for selecting among, for instance, an alarm sound, a melody chime, and silence. An operating lever for the changeover switch extends through the cover to the outside for ease of selection.
    • 一种门关闭器,其能够在相关门打开并且可以安装在现有的开门机构上时发出选定的声音或保持静音。 设置有两个安装在门关闭机构主体的相对端上的盖。 两个盖中的一个承载扬声器,而另一个承载声音发生电路,传感器和切换开关。 切换开关用于在例如闹钟声,旋律钟和静音之间进行选择。 用于切换开关的操作杆通过盖延伸到外部以便于选择。
    • 13. 发明申请
    • Testing method for semiconductor device and testing circuit for semiconductor device
    • 半导体器件的测试方法和半导体器件的测试电路
    • US20060041806A1
    • 2006-02-23
    • US11098411
    • 2005-04-05
    • Kohei OkadaJunji Mori
    • Kohei OkadaJunji Mori
    • G01R31/28
    • G01R31/318594
    • There is provided a testing method for a semiconductor device which has a test object circuit, a non-test object circuit, and a plurality of register circuits which carry out fetching and holding of data based on a clock signal, the semiconductor device including a plurality of first scan chains configured such that the register circuits in the test object circuit are serially connected, and a plurality of second scan chains configured such that the register circuits in the non-test object circuit are serially connected, the testing method including: providing test data to the first and second scan chains, and inputting the clock signal to the first scan chains, not inputting the clock signal to the second scan chains.
    • 提供一种半导体器件的测试方法,其具有测试对象电路,非测试对象电路以及基于时钟信号执行数据取出和保持的多个寄存器电路,该半导体器件包括多个 第一扫描链被配置为使得测试对象电路中的寄存器电路串联,并且多个第二扫描链被配置为使得非测试对象电路中的寄存器电路串联连接,所述测试方法包括:提供测试 数据到第一和第二扫描链,以及将时钟信号输入到第一扫描链,而不是将时钟信号输入到第二扫描链。
    • 15. 发明授权
    • Division circuit using higher radices
    • 分割电路使用较高的radices
    • US5177703A
    • 1993-01-05
    • US796426
    • 1991-11-22
    • Junji Mori
    • Junji Mori
    • G06F7/537G06F7/52G06F7/535
    • G06F7/535
    • A division circuit having a plurality of stages based on a repeat arithmetic operation method, with each stage having: a constant multiplier for multiplying a divisor by a predetermined constant multiple; a carry save type adder (CSA) for performing an addition operation between a dividend and the constant multiple value of the divisor provided from the constant multiplier, then for outputting a sum component and a carry component as a result of the addition operation; shifters for shifting the sum component and the carry component by a shift amount in accordance with a radix, respectively; a carry propagation adder (CPA) for performing an addition operation between the upper bits of the shifted sum component and the shifted carry component obtained by the shifter by predetermined bits; and comparators for outputting a part of a quotient having a plurality of bits by comparing the result obtained by the CPA and the constant multiple value of the divisor, then for determining the value of the constant multiple of the constant multiplier based on the comparison result. In the division circuit, the value of the constant multiple at the following constant multiplier is determined by the output of the comparator and the output of the CPA, the sum component and the carry component obtained by the CSA are provided to a CSA in the following stage, and the dividend and zero in place of the sum component and the carry component are input to the CSA in the first stage.
    • 一种分割电路,具有基于重复算术运算方法的多个级,每级具有:用除数除以预定常数倍的常数乘法器; 进位保存型加法器(CSA),用于执行除数和从常数乘数提供的除数的常数倍数之间的相加运算,然后作为加法运算的结果输出和分量和进位分量; 移位器,用于分别根据基数将和分量和进位分量移位移位量; 一个进位传播加法器(CPA),用于在移位的和分量的高位和由移位器获得的移位的进位分量之间执行预定位的加法运算; 以及比较器,用于通过比较由CPA获得的结果和除数的常数倍数来输出具有多个比特的商的一部分,然后基于比较结果确定常数倍数的常数倍的值。 在除法电路中,以下常数乘法器的常数倍数值由比较器的输出决定,并且CPA的输出,由CSA获得的和分量和进位分量的输出提供给CSA 在第一阶段向CSA输入除数和零代替和分量和进位分量。
    • 18. 发明授权
    • Test facilitating circuit of microprocessor
    • 微处理器测试促进电路
    • US6003142A
    • 1999-12-14
    • US988475
    • 1997-12-10
    • Junji Mori
    • Junji Mori
    • G06F11/22G06F11/267G06F12/08G06F15/78G06F11/00
    • G06F11/2236
    • A test facilitating circuit of a microprocessor has a mode register (11). If data stored in the mode register indicates a test mode, the test facilitating circuit uses a test mode function of a cache memory (1), to execute a test program written in the cache memory irrespective of the resetting of the microprocessor. The test program carries out a built-in test on internal circuits of the microprocessor. Results of the test are stored in the cache memory. After the test, an external tester reads the test results out of the cache memory and examines them.
    • 微处理器的测试促进电路具有模式寄存器(11)。 如果存储在模式寄存器中的数据指示测试模式,则测试便利电路使用高速缓存存储器(1)的测试模式功能来执行写入高速缓冲存储器中的测试程序,而不管微处理器的重置。 测试程序对微处理器的内部电路进行内置测试。 测试结果存储在缓存中。 测试结束后,外部测试人员将测试结果从缓存中读出并进行检查。
    • 19. 发明授权
    • Method and apparatus for branch prediction using branch prediction table
with improved branch prediction effectiveness
    • 使用具有改进的分支预测有效性的分支预测表进行分支预测的方法和装置
    • US5414822A
    • 1995-05-09
    • US863181
    • 1992-04-03
    • Mitsuo SaitoTakeshi AikawaJunji Mori
    • Mitsuo SaitoTakeshi AikawaJunji Mori
    • G06F9/38
    • G06F9/3885G06F9/3806G06F9/3844
    • The branch prediction using a branch prediction table formed by an associative memory which is applicable to a super scalar processor without causing confusion in the branch prediction. The branch prediction uses a branch prediction table for registering entries, each entry including a branching address, a branch target address, and an instruction position indicating a position of the predicted branch instruction in group of instructions to be executed concurrently, or an entry address indicating a position of each entry in the associative memory of the table. A correctness of the predicted branch instruction is checked by using actual branch target address and/or actual instruction position of actual branch instruction encountered in the actual execution of presently fetched instructions. When the predicted branch instruction is incorrect, instructions fetched at a next processing timing are invalidated and the entry in the table is rewritten.
    • 该分支预测使用由适用于超标量处理器的关联存储器形成的分支预测表,而不会导致分支预测中的混淆。 分支预测使用用于登记条目的分支预测表,每个条目包括分支地址,分支目标地址和指示同时执行的指令组中的预测分支指令的位置的指示位置,或指示 每个条目在表的关联记忆中的位置。 通过使用实际分支目标地址和/或在当前取得的指令的实际执行中遇到的实际分支指令的实际指令位置来检查预测分支指令的正确性。 当预测分支指令不正确时,在下一个处理定时取出的指令无效,表中的条目被重写。