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11. 发明申请

US20130038760A1 FRONT-END PIXEL FIXED PATTERN NOISE CORRECTION IN IMAGING ARRAYS HAVING WIDE DYNAMIC RANGE 有权
标题翻译：具有宽动态范围的成像阵列中的前端像素固定图案噪声校正
公开(公告)号：US20130038760A1
公开(公告)日：2013-02-14
申请号：US13206175
申请日：2011-08-09
申请人： Laurent Blanquart , Ying Huang , Joey Shah , David Lawrence Standley
发明人： Laurent Blanquart , Ying Huang , Joey Shah , David Lawrence Standley
IPC分类号： H04N5/217 , G01J1/42
CPC分类号： H04N5/378 , H04N5/365
摘要： Aspects describe front-end pixel fixed pattern noise correction in imaging arrays having wide dynamic range. A photosensor of a first pixel in a first row of an array is reset and a first reset level of the first pixel is measured. The array comprises a plurality of pixels arranged in rows and columns. In response to a result of the first reset level, a reset bus is altered. A feed-forward adjustment of the photosensor of the first pixel is performed to substantially remove fixed-pattern noise. An external readout from the photosensor can occur with substantially all the fixed-pattern noise removed. In some aspects, the adjustment is performed by a switched capacitor block.
摘要翻译：方面描述了具有宽动态范围的成像阵列中的前端像素固定图案噪声校正。阵列的第一行中的第一像素的光电传感器被复位，并且测量第一像素的第一复位电平。阵列包括以行和列排列的多个像素。响应于第一复位电平的结果，复位总线被改变。执行第一像素的光传感器的前馈调整以基本上去除固定图案噪声。可以发生来自光电传感器的外部读出，其中消除了基本上所有的固定图案噪声。在一些方面，调节由开关电容器块执行。

12. 发明授权

US09191598B2 Front-end pixel fixed pattern noise correction in imaging arrays having wide dynamic range 有权
标题翻译：具有宽动态范围的成像阵列中的前端像素固定图案噪声校正
公开(公告)号：US09191598B2
公开(公告)日：2015-11-17
申请号：US13206175
申请日：2011-08-09
申请人： Laurent Blanquart , Ying Huang , Joey Shah , David Lawrence Standley
发明人： Laurent Blanquart , Ying Huang , Joey Shah , David Lawrence Standley
IPC分类号： H04N5/217 , H04N5/378 , H04N5/365
CPC分类号： H04N5/378 , H04N5/365
摘要： Aspects describe front-end pixel fixed pattern noise correction in imaging arrays having wide dynamic range. A photosensor of a first pixel in a first row of an array is reset and a first reset level of the first pixel is measured. The array comprises a plurality of pixels arranged in rows and columns. In response to a result of the first reset level, a reset bus is altered. A feed-forward adjustment of the photosensor of the first pixel is performed to substantially remove fixed-pattern noise. An external readout from the photosensor can occur with substantially all the fixed-pattern noise removed. In some aspects, the adjustment is performed by a switched capacitor block.
摘要翻译：方面描述了具有宽动态范围的成像阵列中的前端像素固定图案噪声校正。阵列的第一行中的第一像素的光电传感器被复位，并且测量第一像素的第一复位电平。阵列包括以行和列排列的多个像素。响应于第一复位电平的结果，复位总线被改变。执行第一像素的光传感器的前馈调整以基本上去除固定图案噪声。可以发生来自光电传感器的外部读出，其中消除了基本上所有的固定图案噪声。在一些方面，调节由开关电容器块执行。

13. 发明授权

US09123602B2 Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects 有权
标题翻译：使用具有最小垂直互连的混合图像传感器的堆叠方案的像素阵列区域优化
公开(公告)号：US09123602B2
公开(公告)日：2015-09-01
申请号：US13471267
申请日：2012-05-14
申请人： Laurent Blanquart
发明人： Laurent Blanquart
IPC分类号： H01L27/00 , H01L23/02 , H01L27/146
CPC分类号： A61B1/051 , A61B1/00009 , A61B1/0676 , H01L24/17 , H01L25/0657 , H01L27/124 , H01L27/146 , H01L27/14601 , H01L27/14603 , H01L27/14609 , H01L27/14618 , H01L27/14634 , H01L27/14636 , H01L27/14638 , H01L27/1464 , H01L27/14641 , H01L27/14643 , H01L27/14689 , H01L27/1469 , H01L31/028 , H01L31/0296 , H01L31/0304 , H01L2924/0002 , H01L2924/381 , H04N5/2256 , H04N5/3742 , H04N5/37455 , H04N5/37457 , H04N5/378 , H04N2005/2255 , H01L2924/00
摘要： Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.
摘要翻译：公开了使用堆叠方案来优化衬底上的像素阵列区域的混合成像传感器的实施例，用于放置具有在堆叠衬底之间的最小垂直互连的相关电路和相关联的特征。还公开了最大化的像素阵列尺寸/裸片尺寸（面积优化）的实施例，并且还公开了为数字成像工业通用的特定应用提供改善的图像质量，改进的功能性和改进的形状因子的优化成像传感器。

14. 发明授权

US08952312B2 Image sensor for endoscopic use 有权
标题翻译：用于内窥镜使用的图像传感器
公开(公告)号：US08952312B2
公开(公告)日：2015-02-10
申请号：US13471446
申请日：2012-05-14
申请人： Laurent Blanquart , Joshua D. Talbert , Jeremiah D. Henley , Donald M. Wichern
发明人： Laurent Blanquart , Joshua D. Talbert , Jeremiah D. Henley , Donald M. Wichern
IPC分类号： H04N7/18 , H01L27/146
CPC分类号： A61B1/051 , A61B1/00009 , A61B1/0676 , H01L24/17 , H01L25/0657 , H01L27/124 , H01L27/146 , H01L27/14601 , H01L27/14603 , H01L27/14609 , H01L27/14618 , H01L27/14634 , H01L27/14636 , H01L27/14638 , H01L27/1464 , H01L27/14641 , H01L27/14643 , H01L27/14689 , H01L27/1469 , H01L31/028 , H01L31/0296 , H01L31/0304 , H01L2924/0002 , H01L2924/381 , H04N5/2256 , H04N5/3742 , H04N5/37455 , H04N5/37457 , H04N5/378 , H04N2005/2255 , H01L2924/00
摘要： An endoscopic device having embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.
摘要翻译：公开了一种具有混合成像传感器的实施例的内窥镜装置，该混合成像传感器使用堆叠方案来优化衬底上的像素阵列区域，用于在叠置的衬底和相关联的特征之间布置具有最小垂直互连的相关电路。还公开了最大化的像素阵列尺寸/裸片尺寸（面积优化）的实施例，并且还公开了为数字成像工业通用的特定应用提供改善的图像质量，改进的功能性和改进的形状因子的优化成像传感器。上述实施例可以包括使用垂直互连的列或子列混合图像传感器中交错ADC或列电路凸块的系统，方法和过程。

15. 发明授权

US08164657B2 Pixel or column fixed pattern noise mitigation using partial or full frame correction with uniform frame rates 有权
标题翻译：使用部分或全帧校正，具有统一的帧速率的像素或列固定模式噪声抑制
公开(公告)号：US08164657B2
公开(公告)日：2012-04-24
申请号：US12163211
申请日：2008-06-27
申请人： Laurent Blanquart
发明人： Laurent Blanquart
IPC分类号： H04N5/217 , H04N5/228 , H04N5/235 , H04N9/64 , H04N5/335
CPC分类号： H04N5/2351 , H04N5/353
摘要： Systems and methods are provided that facilitate mitigating pixel or column fixed pattern noise in a CMOS imaging System-on-Chip (iSoC) sensor. For instance, pixel or column fixed pattern noise can be recognized by gating a pixel array without firing a transfer signal (TX). Inhibiting the transfer signal can cause zero input to be provided to pixels in the pixel array; thus, the sampled output from the pixels under such conditions can be a function of noise. Calibration and correction can thereafter be effectuated. Moreover, uniform frame rates for outputted frames can be yielded irrespective of use of a subset of read out frames for calibration. For example, frames employed for calibration can be replaced in a sequence of outputted frames by copies of stored frames. Further, signal levels can be balanced to account for differences in light integration time, which can result from blocking and unblocking firing of transfer signals.
摘要翻译：提供了系统和方法，其有助于减轻CMOS成像片上系统（iSoC）传感器中的像素或列固定模式噪声。例如，可以通过选通像素阵列而不触发传输信号（TX）来识别像素或列固定图案噪声。抑制传送信号可以使零输入被提供给像素阵列中的像素; 因此，在这种条件下来自像素的采样输出可以是噪声的函数。此后可进行校准和校正。此外，无论使用用于校准的读出帧的子集，都可以产生输出帧的均匀帧速率。例如，用于校准的帧可以通过存储帧的副本以输出帧序列替换。此外，可以平衡信号电平以解决光积分时间的差异，这可能由于传输信号的阻塞和解除阻塞而产生。

16. 发明授权

US07834306B2 Dark current and lag reduction 失效
标题翻译：暗电流和滞后减少
公开(公告)号：US07834306B2
公开(公告)日：2010-11-16
申请号：US12053670
申请日：2008-03-24
申请人： Joey Shah , Laurent Blanquart
发明人： Joey Shah , Laurent Blanquart
IPC分类号： H03F3/08 , H01L27/00 , H04N3/14
CPC分类号： H04N5/378
摘要： The claimed subject matter provides systems and/or methods that facilitate reducing dark current and lag in a CMOS imaging System-on-Chip (iSoC) sensor. For instance, a vertical output driver can output a signal upon a node connected to gates of reset transistors and/or gates of transfer transistors of pixels in the pixel array while operating in rolling shutter mode and/or global shutter mode. Further, a pre-charger can transition a voltage of the node to a first voltage level. Moreover, a booster can further adjust the voltage of the node from the first voltage level to a second voltage level. The booster can have variable drive capability that enables varying operation thereof according to at least one degree of freedom (e.g., speed of the booster proceeding to the second voltage level, frequency of yielding charge to the node, the second voltage level, or timing of the booster and the pre-charger, . . . ).
摘要翻译：所要求保护的主题提供了有助于减少CMOS成像片上系统（iSoC）传感器中的暗电流和滞后的系统和/或方法。例如，垂直输出驱动器可以在以滚动快门模式和/或全局快门模式操作时在连接到像素阵列中的像素的传输晶体管的复位晶体管的栅极和/或栅极的节点上输出信号。此外，预充电器可以将节点的电压转换到第一电压电平。此外，升压器可以进一步将节点的电压从第一电压电平调整到第二电压电平。升压器可以具有可变驱动能力，其能够根据至少一个自由度（例如，升压器进入第二电压电平的速度，向节点产生电荷的频率，第二电压电平或第增压器和预充电器，...）。

17. 发明授权

US09622650B2 System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects 有权
公开(公告)号：US09622650B2
公开(公告)日：2017-04-18
申请号：US13471432
申请日：2012-05-14
申请人： Laurent Blanquart
发明人： Laurent Blanquart
IPC分类号： H01L27/00 , H01J40/14 , A61B1/05 , H01L27/146 , A61B1/00 , H04N5/374 , H04N5/3745 , H04N5/378 , H01L23/00 , A61B1/06 , H04N5/225 , H01L31/028 , H01L31/0296 , H01L31/0304
CPC分类号： A61B1/051 , A61B1/00009 , A61B1/0676 , H01L24/17 , H01L25/0657 , H01L27/124 , H01L27/146 , H01L27/14601 , H01L27/14603 , H01L27/14609 , H01L27/14618 , H01L27/14634 , H01L27/14636 , H01L27/14638 , H01L27/1464 , H01L27/14641 , H01L27/14643 , H01L27/14689 , H01L27/1469 , H01L31/028 , H01L31/0296 , H01L31/0304 , H01L2924/0002 , H01L2924/381 , H04N5/2256 , H04N5/3742 , H04N5/37455 , H04N5/37457 , H04N5/378 , H04N2005/2255 , H01L2924/00
摘要： Embodiments of a hybrid imaging sensor and methods for pixel sub-column data read from the within a pixel array.

18. 发明授权

US08823846B2 Pausing digital readout of an optical sensor array 有权
标题翻译：暂停光学传感器阵列的数字读出
公开(公告)号：US08823846B2
公开(公告)日：2014-09-02
申请号：US13109231
申请日：2011-05-17
申请人： Laurent Blanquart , John Wallner , Manjunath Bhat
发明人： Laurent Blanquart , John Wallner , Manjunath Bhat
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H04N5/3535 , H04N5/374
摘要： Providing for pausing data readout from an optical sensor array is described herein. By way of example, an interruption period can be introduced into a readout cycle of the optical sensor array to suspend readout of data. During the interruption period, other operations related to the optical sensor array can be performed, including operations that are typically detrimental to image quality. Moreover, these operations can be performed while mitigating or avoiding negative impact on the image quality. Thus, greater flexibility is provided for global shutter operations, for instance, potentially improving frame rates and fine control of image exposure, while preserving image quality.
摘要翻译：这里描述了从光学传感器阵列暂停数据读出。作为示例，可以将中断周期引入光学传感器阵列的读出周期以暂停数据的读出。在中断期间，可以执行与光学传感器阵列相关的其它操作，包括通常对图像质量有害的操作。此外，可以在减轻或避免图像质量的负面影响的同时执行这些操作。因此，为全局快门操作提供更大的灵活性，例如，可以在保持图像质量的同时潜在地提高帧速率和图像曝光的精细控制。

19. 发明授权

US08144226B2 Two-by-two pixel structure in an imaging system-on-chip 有权
标题翻译：成像系统芯片中的2×2像素结构
公开(公告)号：US08144226B2
公开(公告)日：2012-03-27
申请号：US11969302
申请日：2008-01-04
申请人： Joey Shah , Laurent Blanquart
发明人： Joey Shah , Laurent Blanquart
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H04N9/045 , H04N5/3742 , H04N5/37457
摘要： The claimed subject matter provides systems and/or methods that facilitate mitigating an impact resulting from mismatch between signal chains in a CMOS imaging System-on-Chip (iSoC) sensor. Two-by-two pixel structures can be a basic building block upon which a pixel array is constructed. Further, each two-by-two pixel structure can be associated with a read bus that carries a sampled signal to a top end and a bottom end of a chip. Moreover, multiplexers at either end of the chip can select a subset of the read buses from which to receive a subset of the sampled signals. Accordingly, pixels in a first color plane can be read, processed, etc. on the same side of the chip (e.g., utilizing a common signal chain), while pixels in at least one second color plane can be read, processed, etc. on the other side of the chip (e.g., employing a differing signal chain).
摘要翻译：所要求保护的主题提供了有助于减轻由CMOS成像片上系统（iSoC）传感器中的信号链之间不匹配引起的影响的系统和/或方法。 2×2像素结构可以是构建像素阵列的基本构建块。此外，每个2×2像素结构可以与将采样信号传送到芯片的顶端和底端的读总线相关联。此外，芯片任一端的多路复用器可以选择读取总线的子集，从中接收采样信号的子集。因此，可以在芯片的同一侧（例如，利用公共信号链）读取，处理等第一颜色平面中的像素，同时可以读取，处理至少一个第二颜色平面中的像素等。在芯片的另一侧（例如，采用不同的信号链）。

20. 发明申请

US20100289580A1 Operational trans-conductance amplifier with output clamp circuit 有权
标题翻译：输出钳位电路的运算放大器
公开(公告)号：US20100289580A1
公开(公告)日：2010-11-18
申请号：US12454320
申请日：2009-05-15
申请人： David Standley , Laurent Blanquart
发明人： David Standley , Laurent Blanquart
IPC分类号： H03F3/45
CPC分类号： H03F1/523 , H03F3/45192 , H03F2200/441 , H03F2203/45636
摘要： An operational trans-conductance amplifier circuit having a voltage clamp circuit. The clamp circuit utilizes low area and power overhead, has a sharp clamp characteristic, and little degradation in the small-signal DC gain at the “knee” of the clamp characteristic. The clamp circuit includes a comparator circuit and a current control circuit. The amplifier and clamp circuits may further include a clamp voltage generator circuit.
摘要翻译：一种具有电压钳位电路的运行的跨导放大器电路。钳位电路利用低面积和功率开销，具有尖锐的钳位特性，并且在钳位特性的“拐点”处的小信号DC增益几乎没有劣化。钳位电路包括比较器电路和电流控制电路。放大器和钳位电路还可以包括钳位电压发生器电路。

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