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11. 发明授权

US07898274B2 Structure of probe 有权
标题翻译：探头结构
公开(公告)号：US07898274B2
公开(公告)日：2011-03-01
申请号：US11745463
申请日：2007-05-08
申请人： Chia-Wei Wu
发明人： Chia-Wei Wu
IPC分类号： G01R31/20
CPC分类号： G01R1/06772 , G01R1/06727 , G01R1/06733
摘要： A split-type probe is used to contact with an object under test to detect an electrical characteristic thereof. The probe provided by the present invention has a contact head used to contact with the object under test, and a first needle body and a second needle body. The first needle body is connected to the contact head to transmit a testing signal to the object under test for performing detection. In addition, the second needle body is also connected to the contact head to transmit a response signal generated by the object under test due to the testing signal to obtain the electrical characteristic of the object under test.
摘要翻译：分离式探头用于与待测物体接触以检测其电气特性。本发明提供的探针具有用于与待测物体接触的接触头，以及第一针体和第二针体。第一针体连接到接触头，以将测试信号传送到被测物体进行检测。此外，第二针体还连接到接触头，以通过测试信号传输由被测物体产生的响应信号，以获得被测物体的电特性。

12. 发明申请

US20090213656A1 FLASH MEMORY HAVING INSULATING LINERS BETWEEN SOURCE/DRAIN LINES AND CHANNELS 有权
标题翻译：在源/排水管线和通道之间具有绝缘衬套的闪存
公开(公告)号：US20090213656A1
公开(公告)日：2009-08-27
申请号：US12038612
申请日：2008-02-27
申请人： Shaw Hung Ku , Teng Hao Yeh , Shih-Chin Lee , Shang-Wei Lin , Chia-Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
发明人： Shaw Hung Ku , Teng Hao Yeh , Shih-Chin Lee , Shang-Wei Lin , Chia-Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
IPC分类号： G11C11/34 , H01L21/8247
CPC分类号： H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.
摘要翻译：存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

13. 发明授权

US07442620B2 Methods for forming a trench isolation structure with rounded corners in a silicon substrate 有权
标题翻译：在硅衬底中形成具有圆角的沟槽隔离结构的方法
公开(公告)号：US07442620B2
公开(公告)日：2008-10-28
申请号：US11423859
申请日：2006-06-13
申请人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wuu Yang
发明人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wuu Yang
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A process for forming STI regions comprises performing an In Situ Steam Generation (ISSG) radical conversion on a SiN liner layer within an STI trench in order to expose the top corner of the trench and simultaneously cause rounding the top corner of a liner oxide layer within the trench. The rounding of the liner oxide layer can prevent thinning of a subsequently formed gate oxide.
摘要翻译：用于形成STI区域的方法包括在STI沟槽内的SiN衬垫层上进行原位蒸汽发生（ISSG）自由基转化，以暴露沟槽的顶角，并且同时引起衬里氧化物层的顶角四周沟渠。衬垫氧化物层的四舍五入可防止随后形成的栅极氧化物的变薄。

14. 发明申请

US20070190797A1 Cleaning method for use in semiconductor device fabrication 有权
标题翻译：用于半导体器件制造的清洁方法
公开(公告)号：US20070190797A1
公开(公告)日：2007-08-16
申请号：US11352547
申请日：2006-02-13
申请人： Chia-Wei Wu , Tuung Luoh , Ling-Wuu Yang , Kuang-Chao Chen
发明人： Chia-Wei Wu , Tuung Luoh , Ling-Wuu Yang , Kuang-Chao Chen
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/7684 , H01L21/02074
摘要： A novel cleaning method for preventing defects and particles resulting from post tungsten etch back or tungsten chemical mechanical polish is provided. The cleaning method comprises providing a stack structure of a semiconductor device including a tungsten plug in a dielectric layer. The tungsten plug has a top excess portion. A surface of the stack structure is then contacted with a cleaning solution comprising hydrogen peroxide. Next, the surface of the stack structure is contacted with dilute hydrofluoric acid. The cleaning solution and hydrofluoric acid are capable of removing the top excess portion and particles on the surface of the stack structure.
摘要翻译：提供了用于防止由钨后蚀刻或钨化学机械抛光引起的缺陷和颗粒的新型清洁方法。该清洁方法包括在电介质层中提供包括钨塞的半导体器件的堆叠结构。钨插头具有顶部多余部分。然后将堆叠结构的表面与包含过氧化氢的清洁溶液接触。接下来，将堆叠结构的表面与稀氢氟酸接触。清洁溶液和氢氟酸能够除去顶部过剩部分和堆叠结构表面上的颗粒。

15. 发明授权

US08211806B2 Method of fabricating integrated circuit with small pitch 有权
标题翻译：制造小间距集成电路的方法
公开(公告)号：US08211806B2
公开(公告)日：2012-07-03
申请号：US11846900
申请日：2007-08-29
申请人： Chia-Wei Wu , Ling-Wu Yang
发明人： Chia-Wei Wu , Ling-Wu Yang
IPC分类号： H01L21/302
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method of manufacturing an integrated circuit with a small pitch comprises providing a second material layer patterned to form at least two features with an opening between the features. The second material layer is formed over a first material layer and the first material layer is over a substrate. The method also comprises providing a first oxide layer to form a first sidewall surrounding each of the features, and providing a second oxide layer over the first sidewalls and the first material layer. A second sidewall is formed surrounding each of the features. The method further comprises providing a conductive layer over the second oxide layer and removing the conductive layer, the second sidewalls and the first material underneath the second sidewalls.
摘要翻译：制造具有小间距的集成电路的方法包括提供图案化以形成具有特征之间的开口的至少两个特征的第二材料层。第二材料层形成在第一材料层上并且第一材料层在衬底之上。该方法还包括提供第一氧化物层以形成围绕每个特征的第一侧壁，以及在第一侧壁和第一材料层之上提供第二氧化物层。形成围绕每个特征的第二侧壁。该方法还包括在第二氧化物层上提供导电层，并移除第二侧壁下方的导电层，第二侧壁和第一材料。

16. 发明授权

US07795891B2 Tester with low signal attenuation 有权
标题翻译：测试仪具有低信号衰减
公开(公告)号：US07795891B2
公开(公告)日：2010-09-14
申请号：US12534868
申请日：2009-08-04
申请人： Chia-Wei Wu
发明人： Chia-Wei Wu
IPC分类号： G01R31/02
CPC分类号： G01R1/06772 , G01R1/06727 , G01R1/06733
摘要： A tester with low signal attenuation and suitable for measuring an electrical characteristic of a subject to be tested includes a circuit board and a first probe. The circuit board has a first surface and a second surface respectively having a first signal transmission line and a second signal transmission line. The first probe has a contact end contacting the subject to be tested and a first signal end and a second signal end respectively connecting the first signal transmission line and the second signal transmission line. The first probe receives a testing signal from the first signal transmission line through the first signal end and transmits the testing signal from the contact end to the subject to be tested, such that the subject to be tested generates a response signal, and the first probe transmits the response signal to the second signal transmission line through the second signal end.
摘要翻译：具有低信号衰减并且适于测量待测试对象的电特性的测试仪包括电路板和第一探针。电路板具有分别具有第一信号传输线和第二信号传输线的第一表面和第二表面。第一探针具有接触端接触被测试对象和分别连接第一信号传输线和第二信号传输线的第一信号端和第二信号端。第一探测器通过第一信号端接收来自第一信号传输线的测试信号，并将测试信号从接触端传送到要测试的对象，使得被测试对象产生响应信号，并且第一探针通过第二信号端将响应信号发送到第二信号传输线。

17. 发明授权

US07776713B2 Etching solution, method of surface modification of semiconductor substrate and method of forming shallow trench isolation 有权
标题翻译：蚀刻溶液，半导体衬底的表面改性方法和形成浅沟槽隔离的方法
公开(公告)号：US07776713B2
公开(公告)日：2010-08-17
申请号：US11806186
申请日：2007-05-30
申请人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wu Yang
发明人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wu Yang
IPC分类号： H01L21/465
CPC分类号： H01L21/30604 , C09K13/08 , H01L21/30608 , H01L21/76232
摘要： An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant and an oxide remover. The semiconductor substrate is oxidized to a semiconductor oxide by the oxidant, and the oxide remover subtracts the semiconductor oxide.
摘要翻译：提供蚀刻溶液，半导体衬底的表面改性方法和形成浅沟槽隔离的方法。蚀刻溶液用于表面改性半导体衬底。蚀刻溶液包括氧化剂和氧化物去除剂。半导体衬底被氧化剂氧化成半导体氧化物，并且氧化物去除器减去半导体氧化物。

18. 发明申请

US20090289649A1 TESTER WITH LOW SIGNAL ATTENUATION 有权
标题翻译：具有低信号衰减的测试仪
公开(公告)号：US20090289649A1
公开(公告)日：2009-11-26
申请号：US12534868
申请日：2009-08-04
申请人： Chia-Wei Wu
发明人： Chia-Wei Wu
IPC分类号： G01R31/26 , G01R31/02
CPC分类号： G01R1/06772 , G01R1/06727 , G01R1/06733
摘要： A tester with low signal attenuation and suitable for measuring an electrical characteristic of a subject to be tested includes a circuit board and a first probe. The circuit board has a first surface and a second surface respectively having a first signal transmission line and a second signal transmission line. The first probe has a contact end contacting the subject to be tested and a first signal end and a second signal end respectively connecting the first signal transmission line and the second signal transmission line. The first probe receives a testing signal from the first signal transmission line through the first signal end and transmits the testing signal from the contact end to the subject to be tested, such that the subject to be tested generates a response signal, and the first probe transmits the response signal to the second signal transmission line through the second signal end.
摘要翻译：具有低信号衰减并且适于测量待测试对象的电特性的测试仪包括电路板和第一探针。电路板具有分别具有第一信号传输线和第二信号传输线的第一表面和第二表面。第一探针具有接触端接触被测试对象和分别连接第一信号传输线和第二信号传输线的第一信号端和第二信号端。第一探测器通过第一信号端接收来自第一信号传输线的测试信号，并将测试信号从接触端传送到要测试的对象，使得被测试对象产生响应信号，并且第一探针通过第二信号端将响应信号发送到第二信号传输线。

19. 发明申请

US20090091983A1 NON-VOLATILE MEMORY STRUCTURE AND ARRAY THEREOF 有权
标题翻译：非易失性存储器结构及其阵列
公开(公告)号：US20090091983A1
公开(公告)日：2009-04-09
申请号：US11866756
申请日：2007-10-03
申请人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
发明人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.
摘要翻译：提供了包括基板，堆叠图案和应力图案的非易失性存储器结构。层叠图案设置在基板上。每个堆叠图案包括电荷存储结构和从底部到顶部的栅极。这里，电荷存储结构至少包括电荷存储层。应力图案分别设置在两个相邻堆叠图案之间的基板上。

20. 发明申请

US20070287260A1 METHODS FOR FORMING AN ISOLATION STRUCTURE IN A SILICON SUBSTRATE 有权
标题翻译：在硅衬底中形成隔离结构的方法
公开(公告)号：US20070287260A1
公开(公告)日：2007-12-13
申请号：US11423859
申请日：2006-06-13
申请人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wuu Yang
发明人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wuu Yang
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A process for forming STI regions comprises performing an In Situ Steam Generation (ISSG) radical conversion on a SiN liner layer within an STI trench in order to expose the top corner of the trench and simultaneously cause rounding the top corner of a liner oxide layer within the trench. The rounding of the liner oxide layer can prevent thinning of a subsequently formed gate oxide.
摘要翻译：用于形成STI区域的方法包括在STI沟槽内的SiN衬垫层上进行原位蒸汽发生（ISSG）自由基转化，以暴露沟槽的顶角，并且同时引起衬里氧化物层的顶角四周沟渠。衬垫氧化物层的四舍五入可防止随后形成的栅极氧化物的变薄。

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