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11. 发明授权

US06876365B1 Signal processing circuit for display device 有权
标题翻译：信号处理电路用于显示设备
公开(公告)号：US06876365B1
公开(公告)日：2005-04-05
申请号：US09604301
申请日：2000-06-26
申请人： Yusuke Tsutsui , Mitsugu Kobayashi , Makoto Kitagawa
发明人： Yusuke Tsutsui , Mitsugu Kobayashi , Makoto Kitagawa
IPC分类号： G06F13/00 , H04N3/14
CPC分类号： G09G3/3688 , G09G3/20 , G09G3/30 , G09G3/3666 , G09G2310/0221 , G09G2310/0275 , G09G2310/0283 , G09G2310/0297 , G09G2310/08 , G09G2340/0492 , G09G2352/00
摘要： An input digital video signal is allotted by a first multiplexer (310) between regions of a display area to be driven in a dividing manner and is sequentially input to a first memory portion (30A) or a second memory portion (30B). Each of the first and second memory portions (30A and 30B) comprises an input-side line memory (32) composed of, for example, 400-stage input side shift register to which said digital video signal is sequentially input, and an output-side line memory (34) for receiving the data transferred in parallel from the input line memory (32) to serially output the stored data from a selected one of output portions (Out1-4) provided at the 320th, 256th or first stage FF34. The output portion of the memory (34) is thus selected by selectors (380A, 380B) in accordance with the number of pixels in the horizontal direction of the LCD panel, such that LCD panels having the different numbers of pixels can be driven with the same structure. The output-side line memory (34) further includes a data shift direction switching circuit. By controlling the switching circuit and selecting the output at the first stage FF34(Out4) in the 400 stages, the data from the output-side line memory (34) can be output in the order opposite to the input order into the input-side line memory (32).
摘要翻译：输入数字视频信号由待分割的驱动的显示区域的区域之间的第一多路复用器（310）分配，并被顺序地输入到第一存储器部分（30A）或第二存储器部分（30B）。第一和第二存储器部分（30A和30B）中的每一个包括由例如顺序地输入所述数字视频信号的400级输入侧移位寄存器构成的输入侧行存储器（32）侧面存储器（34），用于接收从输入行存储器（32）并行传送的数据，以便从设置在第320，256或第一级FF34的输出部分（Out1-4）中选择的一个输出存储的数据。因此，存储器（34）的输出部分根据LCD面板的水平方向的像素数由选择器（380A，380B）选择，使得具有不同像素数的LCD面板可以用相同的结构。输出侧线存储器（34）还包括数据移位方向切换电路。通过控制开关电路并在400级中选择第一级FF34（Out4）的输出，来自输出侧行存储器（34）的数据可以以与输入顺序相反的顺序输出到输入侧行存储器（32）。

12. 发明授权

US5990855A Image information process apparatus for causing a display to display continuous tones in a pseudo manner 失效
标题翻译：用于使显示器以伪方式显示连续色调的图像信息处理装置
公开(公告)号：US5990855A
公开(公告)日：1999-11-23
申请号：US813465
申请日：1997-03-10
申请人： Mitsugu Kobayashi , Hisao Uehara , Makoto Kitagawa
发明人： Mitsugu Kobayashi , Hisao Uehara , Makoto Kitagawa
IPC分类号： G09G3/20 , G09G3/36 , H04N5/66 , H04N9/30
CPC分类号： G09G3/2059 , G09G2360/16 , G09G3/3611 , H04N5/66 , H04N9/30
摘要： There is provided an image information process apparatus to be applied to a display for displaying bit image display data for each pixel, for enabling the display to display continuous tones in an error diffusion manner based on P bit image data, P being larger than L. This apparatus includes a plurality of adding circuits to which a plurality of P bit image data are concurrently supplied. A predetermined lower bit of an added result at respective adding circuits is used as error data supplied to the next adjacent adding circuit. An error data holding circuit holds a predetermined lower bit of an output from an adding circuit corresponding to the last column pixel in image data supplied. It then supplies the lower bit held to an adding circuit corresponding to the top front column pixel of the image data supplied. With this arrangement, a display which is capable of displaying images based on digital data of a limited number of bits displays in a pseudo manner continuous tones expressed using a higher number of bits than the limited number. In addition, performance and processing speed of image information processing are improved.
摘要翻译：提供了一种应用于显示器的图像信息处理装置，用于显示每个像素的位图像显示数据，以使得显示器能够以P位图像数据P大于L的方式以误差扩散方式显示连续色调。该装置包括多个附加电路，多个P位图像数据被同时提供给该多个加法电路。作为向下一个相邻加法电路提供的误差数据，使用各加法电路的相加结果的预定的低位。误差数据保持电路保持来自与提供的图像数据中的最后列像素对应的加法电路的输出的预定的低位。然后，将保持的低位提供给与提供的图像数据的顶部前列像素相对应的加法电路。利用这种布置，能够以有限位数的数字数据显示图像的显示器以伪限制的数量显示以连续色调的连续色调。此外，提高了图像信息处理的性能和处理速度。

13. 发明授权

US07728805B2 Liquid crystal display capable of making flicker difficult to be observed and reducing power consumption 失效
标题翻译：能够使闪烁的液晶显示器难以观察并降低功耗
公开(公告)号：US07728805B2
公开(公告)日：2010-06-01
申请号：US11283045
申请日：2005-11-21
申请人： Tamotsu Uekuri , Yusuke Tsutsui , Makoto Kitagawa
发明人： Tamotsu Uekuri , Yusuke Tsutsui , Makoto Kitagawa
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3614 , G09G3/3677 , G09G2300/0876 , G09G2310/06
摘要： A display capable of rendering flickering hard to visually recognize, reducing power consumption and simplifying the structure of a circuit for negatively/positively reversing an image is provided. This display comprises a plurality of drain lines and a plurality of gate lines, a first pixel portion and a second pixel portion each including a subsidiary capacitor having a first electrode and a second electrode and a first subsidiary capacitance line and a second subsidiary capacitance line connected to the subsidiary capacitors of the first pixel portion and the second pixel portion respectively. The display also comprises a signal supply circuit supplying either a first signal or a second signal for negatively/positively reversing an image to the first subsidiary capacitance line of the first pixel portion when displaying the image while supplying either a third signal or a fourth signal for negatively/positively reversing the image to the second subsidiary capacitance line of the second pixel portion when reversing the image.
摘要翻译：本发明提供一种显示器，其能够呈现出难以视觉识别的闪烁，降低功耗并简化电路的结构，从而使/否正反转图像。该显示器包括多个漏极线和多条栅极线，第一像素部分和第二像素部分，每个包括具有第一电极和第二电极的辅助电容器和第二辅助电容线路以及连接到第二辅助电容线路的第二像素部分分别到第一像素部分和第二像素部分的辅助电容器。显示器还包括信号供给电路，当显示图像时，向第一像素部分的第一辅助电容线提供第一信号或第二信号，用于负/正反转图像，同时提供第三信号或第四信号当图像反转时，负/正反转图像到第二像素部分的第二辅助电容线。

14. 发明授权

US07190381B2 Liquid crystal display device and adjusting method of the same 有权
标题翻译：液晶显示装置及其调整方法相同
公开(公告)号：US07190381B2
公开(公告)日：2007-03-13
申请号：US10462813
申请日：2003-06-17
申请人： Yusuke Tsutsui , Makoto Kitagawa , Mitsugu Kobayashi
发明人： Yusuke Tsutsui , Makoto Kitagawa , Mitsugu Kobayashi
IPC分类号： G09G5/00
CPC分类号： G09G3/3655 , G09G3/006 , G09G5/003 , G09G2300/08 , G09G2320/0223 , G09G2320/0693 , G09G2370/042 , Y10S345/904
摘要： A liquid crystal display device has a liquid crystal panel, a DA converter for generating a common electrode signal to be applied to a common electrode of a liquid crystal, and a non-volatile memory for encoding an optimum value of the common electrode signal into an ID code and storing the ID code therein. The DA converter generates the optimum common electrode signal corresponding to the ID code read out from the non-volatile memory. A liquid crystal panel manufacturer ships the liquid crystal panel in which the optimum value of the common electrode signal is encoded into the ID code and stored in the non-volatile memory in an inspecting process. The assembling manufacturer using the liquid crystal panel can easily set the optimum value of the common electrode signal. Furthermore, the liquid crystal display device has a CPU decoding the ID code read out from the non-volatile memory. Alternatively, it is possible to supply a data of a value of the common electrode signal to a user of the liquid crystal. The user adjusts the common electrode signal generating circuit by using the data of the value of the common electrode signal.
摘要翻译：液晶显示装置具有：液晶面板，用于产生要施加到液晶的公共电极的公共电极信号的DA转换器;以及用于将公共电极信号的最佳值编码为 ID代码并存储其中的ID代码。 DA转换器产生对应于从非易失性存储器读出的ID码的最佳公共电极信号。在检查过程中，液晶面板制造商将公共电极信号的最佳值编码为ID代码并存储在非易失性存储器中的液晶面板。使用液晶面板的组装制造商可以容易地设定公共电极信号的最佳值。此外，液晶显示装置具有对从非易失性存储器读出的ID码进行解码的CPU。或者，可以向液晶的用户提供公共电极信号的值的数据。用户通过使用公共电极信号的值的数据来调整公共电极信号发生电路。

15. 发明授权

US08379430B2 Memory device and method of reading memory device 失效
标题翻译：存储器件和读取存储器件的方法
公开(公告)号：US08379430B2
公开(公告)日：2013-02-19
申请号：US12923978
申请日：2010-10-19
申请人： Makoto Kitagawa , Tsunenori Shiimoto , Hiroshi Yoshihara
发明人： Makoto Kitagawa , Tsunenori Shiimoto , Hiroshi Yoshihara
IPC分类号： G11C11/00 , G11C7/02
CPC分类号： G11C13/004 , G11C13/0007 , G11C13/0061 , G11C2013/0054 , G11C2213/11 , G11C2213/56 , G11C2213/79
摘要： A memory device includes: a memory unit in which an electric charge discharging rate between two electrodes is different in accordance with logic of stored information; a sense amplifier that detects the logic of the information by comparing a discharge electric potential of a wiring to which one electrode of the memory unit is connected with a reference electric potential; and a replica circuit that has a replica unit emulating the memory unit and controls a sense timing of the sense amplifier in accordance with a discharge rate of the replica unit.
摘要翻译：存储装置包括：存储单元，其中两个电极之间的电荷放电速率根据所存储信息的逻辑而不同; 读出放大器，通过将存储单元的一个电极与其连接的布线的放电电位与参考电位进行比较来检测信息的逻辑; 以及复制电路，其具有仿真存储器单元的复制单元，并且根据复制单元的放电速率来控制读出放大器的感测时序。

16. 发明申请

US20120218809A1 STORAGE APPARATUS AND OPERATION METHOD FOR OPERATING THE SAME 有权
标题翻译：存储装置和操作方法
公开(公告)号：US20120218809A1
公开(公告)日：2012-08-30
申请号：US13397282
申请日：2012-02-15
申请人： Makoto Kitagawa , Tsunenori Shiimoto , Tomohito Tsushima
发明人： Makoto Kitagawa , Tsunenori Shiimoto , Tomohito Tsushima
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2213/79
摘要： A storage apparatus includes: a plurality of storage elements configured to have the resistance state thereof changed in accordance with an applied voltage; and a drive portion configured to perform a resistance change operation and a read operation, the resistance change operation involving writing or erasing information to or from the storage elements by changing the resistance state thereof, the read operation involving reading the information from the storage elements; wherein the drive portion includes an amplifier configured to output a read signal upon execution of the read operation, a constant current load, and a control portion configured to perform the resistance change operation and a direct verify operation on the storage elements, the direct verify operation involving carrying out, subsequent to the resistance change operation, the read operation for verifying whether the writing or erasing of the information to or from the storage elements has been normally accomplished.
摘要翻译：存储装置包括：多个存储元件，其被配置为根据施加的电压使其电阻状态发生变化; 以及驱动部，被配置为执行电阻变化操作和读取操作，所述电阻改变操作涉及通过改变其电阻状态来从存储元件写入或擦除信息，所述读取操作涉及从存储元件读取信息; 其特征在于，所述驱动部具有：放大器，被配置为在执行所述读取操作时输出读取信号;恒定电流负载;以及被配置为对所述存储元件执行电阻变化操作和直接验证操作的控制部，所述直接验证操作涉及在电阻变化操作之后进行用于验证是否正常地完成对存储元件的写入或擦除信息的读取操作。

17. 发明授权

US08102716B2 Nonvolatile semiconductor memory device and method for performing verify write operation on the same 有权
标题翻译：非易失性半导体存储器件及其执行验证写入操作的方法
公开(公告)号：US08102716B2
公开(公告)日：2012-01-24
申请号：US12654783
申请日：2010-01-04
申请人： Tsunenori Shiimoto , Makoto Kitagawa , Tomohito Tsushima
发明人： Tsunenori Shiimoto , Makoto Kitagawa , Tomohito Tsushima
IPC分类号： G11C11/34
CPC分类号： G11C13/0011 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0078 , G11C2013/0088 , G11C2213/11 , G11C2213/34 , G11C2213/56 , G11C2213/79
摘要： Disclosed herein is a nonvolatile semiconductor memory device including a plurality of memory cells; and a driver circuit configured to perform a verify write operation in a cycle including selecting from an array of the plurality of memory cells a predetermined number of memory cells constituting a write cell unit, writing data collectively to the predetermined number of memory cells, and verifying the written data, the driver circuit further performing the verify write operation repeatedly until all memory cells within the write cell unit are found to have passed the verification.
摘要翻译：这里公开了一种包括多个存储单元的非易失性半导体存储器件; 以及驱动电路，被配置为在循环中执行验证写入操作，包括从多个存储器单元的阵列中选择构成写入单元单元的预定数量的存储单元，将数据共同地写入预定数量的存储单元，以及验证写入的数据，驱动器电路进一步执行验证写入操作，直到发现写入单元单元内的所有存储单元已经通过验证。

18. 发明申请

US20110305068A1 RESISTANCE RANDOM ACCESS CHANGE MEMORY DEVICE 审中-公开
标题翻译：电阻随机访问更改存储器件
公开(公告)号：US20110305068A1
公开(公告)日：2011-12-15
申请号：US13116590
申请日：2011-05-26
申请人： Makoto Kitagawa , Tsunenori Shiimoto , Hiroshi Yoshihara
发明人： Makoto Kitagawa , Tsunenori Shiimoto , Hiroshi Yoshihara
IPC分类号： G11C11/00
CPC分类号： H01L45/085 , G11C13/0026 , G11C13/0069 , G11C2213/79 , G11C2213/82 , H01L27/2436 , H01L27/2472 , H01L45/1233 , H01L45/1266 , H01L45/145
摘要： A resistance random access change memory device includes: a memory cell array in which plural memory cells having current paths with series-connected access transistors and variable resistive elements are two-dimensionally arranged; plural bit lines that connect one ends of the current paths; plural source lines that connect the other ends of the current paths; and plural word lines that control conduction and non-conduction of the access transistors, wherein bit line contacts are shared between two memory cells to which the word lines are adjacently provided, and pairs of memory cells are formed, all of the pairs of memory cells connected to the adjacent two bit lines are connected to the corresponding source lines via individual source line contacts, and the source lines are formed by a wiring layer upper than that of the bit lines with a larger pitch than that of the bit lines.
摘要翻译：电阻随机存取改变存储器件包括：存储单元阵列，其中具有串联连接的存取晶体管和可变电阻元件的电流路径的多个存储单元被二维布置; 连接当前路径的一端的多个位线; 连接当前路径的另一端的多条源极线; 以及控制存取晶体管的导通和非导通的多个字线，其中位线接触在相邻设置有字线的两个存储单元之间共享，并且形成存储单元对，所有存储单元对连接到相邻的两条位线通过各个源极线接触连接到相应的源极线，并且源极线由比位线的间距高于位线的布线层形成。

19. 发明申请

US20110026332A1 Semiconductor memory device and its operation method 失效
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20110026332A1
公开(公告)日：2011-02-03
申请号：US12805089
申请日：2010-07-12
申请人： Makoto Kitagawa
发明人： Makoto Kitagawa
IPC分类号： G11C7/10
CPC分类号： G11C7/12 , G11C7/08 , G11C13/0011 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/009 , G11C2211/5642 , G11C2213/79
摘要： Disclosed herein is a semiconductor memory device including: a bit line and a sense line; a data storage element having a data storage state changing in accordance with a voltage applied to the bit line; a first switch for controlling connection of the sense line to the bit line; a data latch circuit having a second data holding node and a first data holding node connected to the sense line; and a second switch for controlling connection of the second data holding node of the data latch circuit to the bit line.
摘要翻译：本文公开了一种半导体存储器件，包括：位线和感测线; 数据存储元件，其具有根据施加到所述位线的电压而改变的数据存储状态; 用于控制感测线与位线的连接的第一开关; 数据锁存电路，具有第二数据保持节点和连接到感测线的第一数据保持节点; 以及用于控制数据锁存电路的第二数据保持节点与位线的连接的第二开关。

20. 发明申请

US20100195370A1 Nonvolatile semiconductor memory device and method for performing verify write operation on the same 有权
标题翻译：非易失性半导体存储器件及其执行验证写入操作的方法
公开(公告)号：US20100195370A1
公开(公告)日：2010-08-05
申请号：US12654783
申请日：2010-01-04
申请人： Tsunenori Shiimoto , Makoto Kitagawa , Tomohito Tsushima
发明人： Tsunenori Shiimoto , Makoto Kitagawa , Tomohito Tsushima
IPC分类号： G11C11/00 , G11C8/00 , G11C7/00
CPC分类号： G11C13/0011 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0078 , G11C2013/0088 , G11C2213/11 , G11C2213/34 , G11C2213/56 , G11C2213/79
摘要： Disclosed herein is a nonvolatile semiconductor memory device including a plurality of memory cells; and a driver circuit configured to perform a verify write operation in a cycle including selecting from an array of the plurality of memory cells a predetermined number of memory cells constituting a write cell unit, writing data collectively to the predetermined number of memory cells, and verifying the written data, the driver circuit further performing the verify write operation repeatedly until all memory cells within the write cell unit are found to have passed the verification.
摘要翻译：这里公开了一种包括多个存储单元的非易失性半导体存储器件; 以及驱动电路，被配置为在循环中执行验证写入操作，包括从多个存储器单元的阵列中选择构成写入单元单元的预定数量的存储单元，将数据共同地写入预定数量的存储单元，以及验证写入的数据，驱动器电路进一步执行验证写入操作，直到发现写入单元单元内的所有存储单元已经通过验证。

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