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11. 发明授权

US06496430B2 Semiconductor memory circuit having selective redundant memory cells 有权
标题翻译：具有选择性冗余存储单元的半导体存储器电路
公开(公告)号：US06496430B2
公开(公告)日：2002-12-17
申请号：US10131221
申请日：2002-04-25
申请人： Tadao Aikawa , Takaaki Suzuki , Yasuharu Sato , Hiroyuki Kobayashi
发明人： Tadao Aikawa , Takaaki Suzuki , Yasuharu Sato , Hiroyuki Kobayashi
IPC分类号： G11C2900
CPC分类号： G11C29/808
摘要： A semiconductor memory circuit includes a plurality of memory cell arrays arranged in rows and columns. A decoder circuit selects a predetermined number of memory cell arrays from among the plurality of the memory cell arrays. Sense amplifiers sense data read from selected memory cell arrays. The plurality of memory cell arrays are grouped into a first type of memory cell arrays each having a redundant memory cell and a second type of memory cell arrays each having no redundant memory cell.
摘要翻译：半导体存储器电路包括以行和列排列的多个存储单元阵列。解码器电路从多个存储单元阵列中选择预定数量的存储单元阵列。感测放大器感测从选定的存储单元阵列读取的数据。多个存储单元阵列被分组成第一类型的存储单元阵列，每个存储单元阵列具有冗余存储单元和每个不具有冗余存储单元的第二类型存储单元阵列。

12. 发明授权

US06498522B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06498522B2
公开(公告)日：2002-12-24
申请号：US09833045
申请日：2001-04-12
申请人： Hitoshi Ikeda , Shinya Fujioka , Yasuharu Sato , Yasurou Matsuzaki
发明人： Hitoshi Ikeda , Shinya Fujioka , Yasuharu Sato , Yasurou Matsuzaki
IPC分类号： H03L700
CPC分类号： G11C7/1084 , G11C7/1072 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222
摘要： The invention relates to a clock synchronous type semiconductor device that accepts an input signal inputted from the exterior in synchronization with a clock signal. The semiconductor device according to the invention includes an input signal receiving unit that receives an input signal inputted from the exterior, where the receiving is done in synchronization with a clock signal; a clock timing selecting unit for outputting a clock selecting signal; and a clock generating unit that, in response to receiving a clock selecting signal and an external clock signal, generates a clock signal at a predetermined timing which corresponds to a signal level of the clock selecting signal, and outputs the clock signal to the input signal receiving unit, wherein it is possible to securely accept an input signal regardless of the frequency of the external clock signal.
摘要翻译：本发明涉及一种时钟同步型半导体器件，其与时钟信号同步地接收从外部输入的输入信号。根据本发明的半导体器件包括输入信号接收单元，其接收从外部输入的输入信号，其中接收与时钟信号同步完成; 时钟定时选择单元，用于输出时钟选择信号; 以及时钟发生单元，响应于接收到时钟选择信号和外部时钟信号，在与时钟选择信号的信号电平相对应的预定定时产生时钟信号，并将时钟信号输出到输入信号接收单元，其中无论外部时钟信号的频率如何，都可以安全地接受输入信号。

13. 发明授权

US07907434B2 Semiconductor apparatus having a large-size bus connection 有权
标题翻译：具有大尺寸总线连接的半导体装置
公开(公告)号：US07907434B2
公开(公告)日：2011-03-15
申请号：US11984932
申请日：2007-11-26
申请人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
发明人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C5/00 , G11C5/04 , G11C5/063 , H01L25/0652 , H01L25/0657 , H01L27/105 , H01L2224/48091 , H01L2225/0651 , H01L2225/06513 , H01L2225/06562 , H01L2924/13091 , H04L12/40 , H04L12/4625 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.
摘要翻译：在本发明的半导体装置中，设置有多个电路部件。第一条总线将电路组件互连。第二总线将电路组件互连。当从一个电路部件发送信号到另一个电路部件时，切换单元输出使每个电路部件选择第一总线和第二总线中的一个的选择信号。第二个总线的大小大于第一个总线的大小。

14. 发明申请

US20080142847A1 Semiconductor apparatus having a large-size bus connection 有权
标题翻译：具有大尺寸总线连接的半导体装置
公开(公告)号：US20080142847A1
公开(公告)日：2008-06-19
申请号：US11984932
申请日：2007-11-26
申请人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
发明人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
IPC分类号： H01L23/50
CPC分类号： G11C5/06 , G11C5/00 , G11C5/04 , G11C5/063 , H01L25/0652 , H01L25/0657 , H01L27/105 , H01L2224/48091 , H01L2225/0651 , H01L2225/06513 , H01L2225/06562 , H01L2924/13091 , H04L12/40 , H04L12/4625 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.
摘要翻译：在本发明的半导体装置中，设置有多个电路部件。第一条总线将电路组件互连。第二总线将电路组件互连。当从一个电路部件发送信号到另一个电路部件时，切换单元输出使每个电路部件选择第一总线和第二总线中的一个的选择信号。第二个总线的大小大于第一个总线的大小。

15. 发明授权

US06727533B2 Semiconductor apparatus having a large-size bus connection 有权
公开(公告)号：US06727533B2
公开(公告)日：2004-04-27
申请号：US09956973
申请日：2001-09-21
申请人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
发明人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
IPC分类号： H01L31112
CPC分类号： G11C5/06 , G11C5/00 , G11C5/04 , G11C5/063 , H01L25/0652 , H01L25/0657 , H01L27/105 , H01L2224/48091 , H01L2225/0651 , H01L2225/06513 , H01L2225/06562 , H01L2924/13091 , H04L12/40 , H04L12/4625 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

16. 发明授权

US06715115B1 Semiconductor integrated circuit device capable of outputting leading data of a series of multiple burst-readout data without delay 有权
标题翻译：半导体集成电路装置能够不延迟地输出一连串的多脉冲串读出数据的引导数据
公开(公告)号：US06715115B1
公开(公告)日：2004-03-30
申请号：US09615953
申请日：2000-07-13
申请人： Tadao Aikawa , Yasuharu Sato
发明人： Tadao Aikawa , Yasuharu Sato
IPC分类号： G11C2900
CPC分类号： G11C29/1201 , G11C7/1027 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C29/12 , G11C2207/105 , G11C2207/107
摘要： A semiconductor device including a parallel to serial conversion circuit that receives first through nth data (where n is an integer greater than or equal to 2), together with (n+1)th data, in parallel to each other, and that outputs the first through nth data in series in this order via first through nth paths in a first operating mode, while it outputs the (n+1)th data via one of the second through nth paths in a second operation mode. An output control circuit is connected to the parallel to serial conversion circuit via the first through nth paths, the output control circuit successively outputting the first through nth data in the first operating mode, and outputting only the (n+1)th data supplied from the parallel to serial conversion circuit in the second operating mode.
摘要翻译：包括并行到串行转换电路的半导体器件与第（n + 1）个数据并行地接收第一至第n个数据（其中n是大于或等于2的整数），并且在第一操作模式中，通过第一至第n路径以该顺序依次输出第一至第n个数据，同时通过第二至第n个数据中的一个输出第（n + 1）个数据，第二操作模式中的路径。输出控制电路经由第一至第n路连接到并行到串行转换电路，输出控制电路在第一操作模式中连续地输出第一至第n个数据，并且仅输出第（n + 1）个在第二操作模式中从并行到串行转换电路提供的数据。

17. 发明授权

US06192004B1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06192004B1
公开(公告)日：2001-02-20
申请号：US09559743
申请日：2000-04-27
申请人： Tadao Aikawa , Yasuharu Sato
发明人： Tadao Aikawa , Yasuharu Sato
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22 , H03K5/1534
摘要： A clock pulse generator generates a plurality of clock pulses which has different phases during one cycle of a reference clock signal supplied from the exterior. A timing setting circuit sets a latency, which is a number of clock cycles from a start of a read operation to an output of read data, at a number which is divisible by one n-th (n=2, 3, 4 . . . ) of a cycle of the reference clock signal and outputs latency information according to the set latency. An output controlling pulse switching circuit respectively outputs each of the clock pulses as a predetermined output controlling pulse in accordance with the latency information. In other words, a plurality of the output controlling pulses are switched according to the latency information. In synchronization with each of the output controlling pulses, a data outputting circuit sequentially and respectively converts parallel data, read from a plurality of memory cells stored with data, into serial data and respectively outputs the converted serial data during the predetermined period according to the latency. No matter what timing of the reference clock signal the latency might be set at, therefore, the serial data can be reliably outputted without switching the parallel data. The data are outputted at high speed because the parallel data need not be switched.
摘要翻译：时钟脉冲发生器在从外部提供的参考时钟信号的一个周期期间产生具有不同相位的多个时钟脉冲。定时设定电路将从读取操作开始到读取数据的输出的时钟周期数设定为可以被第n个（n = 2,3,4，...）整除的数字。），并且根据设定的等待时间输出等待时间信息。输出控制脉冲切换电路根据等待时间信息分别输出每个时钟脉冲作为预定的输出控制脉冲。换句话说，根据等待时间信息来切换多个输出控制脉冲。与每个输出控制脉冲同步，数据输出电路依次分别将从数据存储的多个存储单元中读取的并行数据转换为串行数据，并根据延迟分别在预定时段内输出转换后的串行数据。无论参考时钟信号的时序如何，延迟可能被设置，因此，可以可靠地输出串行数据，而无需切换并行数据。由于不需要切换并行数据，因此高速输出数据。

18. 发明授权

US07317241B2 Semiconductor apparatus having a large-size bus connection 有权
公开(公告)号：US07317241B2
公开(公告)日：2008-01-08
申请号：US11143649
申请日：2005-06-03
申请人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
发明人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
IPC分类号： H01L23/58
CPC分类号： G11C5/06 , G11C5/00 , G11C5/04 , G11C5/063 , H01L25/0652 , H01L25/0657 , H01L27/105 , H01L2224/48091 , H01L2225/0651 , H01L2225/06513 , H01L2225/06562 , H01L2924/13091 , H04L12/40 , H04L12/4625 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

19. 发明申请

US20050218432A1 Semiconductor apparatus having a large-size bus connection 有权
公开(公告)号：US20050218432A1
公开(公告)日：2005-10-06
申请号：US11143649
申请日：2005-06-03
申请人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
发明人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
IPC分类号： G11C5/00 , G11C5/06 , H01L25/065 , H01L27/105 , H01L29/80 , H01L31/0336 , H01L31/109 , H01L31/112 , H04L12/46
CPC分类号： G11C5/06 , G11C5/00 , G11C5/04 , G11C5/063 , H01L25/0652 , H01L25/0657 , H01L27/105 , H01L2224/48091 , H01L2225/0651 , H01L2225/06513 , H01L2225/06562 , H01L2924/13091 , H04L12/40 , H04L12/4625 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

20. 发明授权

US07808806B2 Semiconductor apparatus having a large-size bus connection 有权
公开(公告)号：US07808806B2
公开(公告)日：2010-10-05
申请号：US11984932
申请日：2007-11-26
申请人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
发明人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
IPC分类号： G11C5/06
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

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