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11. 发明授权

US08645638B2 Shared single-access memory with management of multiple parallel requests 有权
标题翻译：具有管理多个并行请求的共享单访问存储器
公开(公告)号：US08645638B2
公开(公告)日：2014-02-04
申请号：US13466057
申请日：2012-05-07
申请人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
发明人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/084 , Y02D10/13
摘要： A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.
摘要翻译：多线程处理器中的并发线程使用内存。任何可寻址的存储位置都可以由任何并发线程访问，但一次只能访问一个位置。存储器耦合到并行处理引擎，其产生一组并行存储器访问请求，每个指定对于不同请求可能相同或不同的目标地址。序列化逻辑选择一个目标地址，并确定哪个请求指定所选择的目标地址。允许所有这些请求并行进行，而其他请求被推迟。可以通过序列化逻辑重新生成和处理延迟请求，以便通过一次访问组中的每个不同的目标地址来满足一组请求。

12. 发明授权

US08190669B1 Multipurpose arithmetic functional unit 有权
标题翻译：多功能算术功能单元
公开(公告)号：US08190669B1
公开(公告)日：2012-05-29
申请号：US10970253
申请日：2004-10-20
申请人： Stuart F. Oberman , Ming Y. Siu
发明人： Stuart F. Oberman , Ming Y. Siu
IPC分类号： G06F7/44
CPC分类号： G06F7/44 , G06F1/035 , G06F7/5443 , G06F9/3895 , G06F2101/04 , G06F2101/08 , G06F2101/10 , G06F2101/12
摘要： Multipurpose arithmetic functional units can perform planar attribute interpolation and unary function approximation operations. In one embodiment, planar interpolation operations for coordinates (x, y) are executed by computing A*x+B*y+C, and unary function approximation operations for operand x are executed by computing F2(xb)*xh2+F1(xb)*xh+F0(xb), where xh=x−xb. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for both classes of operations.
摘要翻译：多用途算术功能单元可以执行平面属性插值和一元函数近似运算。在一个实施例中，通过计算A * x + B * y + C来执行坐标（x，y）的平面内插操作，并且通过计算F2（xb）* xh2 + F1（xb）来执行操作数x的一元函数近似运算）* xh + F0（xb），其中xh = x-xb。共享乘法器和加法器电路有利地用于实现两类操作的乘积和求和运算。

13. 发明授权

US08037119B1 Multipurpose functional unit with single-precision and double-precision operations 有权
标题翻译：具有单精度和双精度运算功能的多用途功能单元
公开(公告)号：US08037119B1
公开(公告)日：2011-10-11
申请号：US11359353
申请日：2006-02-21
申请人： Stuart F. Oberman , Ming Y. Siu
发明人： Stuart F. Oberman , Ming Y. Siu
IPC分类号： G06F7/44
CPC分类号： G06F7/4876 , G06F7/5324 , G06F7/57 , G06F17/10
摘要： A multipurpose arithmetic functional unit selectably performs planar attribute interpolation, unary function approximation, and double-precision arithmetic. In one embodiment, planar interpolation operations for coordinates (x, y) are executed by computing A*x+B*y+C, and unary function approximation operations for operand x are executed by computing F2(xb)*xh2+F1(xb)*xh+F0(xb), where xh=x−xb. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for unary function approximation and planar interpolation; the same multipliers and adders are also leveraged to implement double-precision multiplication and addition.
摘要翻译：多用途算术功能单元可选地执行平面属性插值，一元函数近似和双精度算术。在一个实施例中，通过计算A * x + B * y + C来执行坐标（x，y）的平面内插操作，并且通过计算F2（xb）* xh2 + F1（xb）来执行操作数x的一元函数近似运算）* xh + F0（xb），其中xh = x-xb。共享乘法器和加法器电路有利地用于实现一元函数近似和平面内插的乘积和求和运算; 同样的乘法器和加法器也被用来实现双精度乘法和加法。

14. 发明授权

US07680988B1 Single interconnect providing read and write access to a memory shared by concurrent threads 有权
标题翻译：单一互连提供对并发线程共享的内存的读写访问
公开(公告)号：US07680988B1
公开(公告)日：2010-03-16
申请号：US11554563
申请日：2006-10-30
申请人： John R. Nickolls , Brett W. Coon , Ming Y. Siu , Stuart F. Oberman , Samuel Liu
发明人： John R. Nickolls , Brett W. Coon , Ming Y. Siu , Stuart F. Oberman , Samuel Liu
IPC分类号： G06F13/16
CPC分类号： G06F12/084 , G06F9/544 , G06F15/167 , Y02D10/13
摘要： A shared memory is usable by concurrent threads in a multithreaded processor, with any addressable storage location in the shared memory being readable and writeable by any of the threads. Processing engines that execute the threads are coupled to the shared memory via an interconnect that transfers data in only one direction (e.g., from the shared memory to the processing engines); the same interconnect supports both read and write operations. The interconnect advantageously supports multiple parallel read or write operations.
摘要翻译：共享存储器可由多线程处理器中的并发线程使用，共享存储器中的任何可寻址存储位置可由任何线程读取和写入。执行线程的处理引擎通过仅在一个方向（例如，从共享存储器到处理引擎）传送数据的互连来耦合到共享存储器; 相同的互连支持读写操作。互连有利地支持多个并行读或写操作。

15. 发明申请

US20120221808A1 SHARED SINGLE-ACCESS MEMORY WITH MANAGEMENT OF MULTIPLE PARALLEL REQUESTS 有权
标题翻译：具有多个并行请求管理的共享单访存储器
公开(公告)号：US20120221808A1
公开(公告)日：2012-08-30
申请号：US13466057
申请日：2012-05-07
申请人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
发明人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , Y02D10/13
摘要： A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.
摘要翻译：多线程处理器中的并发线程使用内存。任何可寻址的存储位置都可以由任何并发线程访问，但一次只能访问一个位置。存储器耦合到并行处理引擎，其产生一组并行存储器访问请求，每个指定对于不同请求可能相同或不同的目标地址。序列化逻辑选择一个目标地址，并确定哪个请求指定所选择的目标地址。允许所有这些请求并行进行，而其他请求被推迟。可以通过序列化逻辑重新生成和处理延迟请求，以便通过一次访问组中的每个不同的目标地址来满足一组请求。

16. 发明授权

US08225076B1 Scoreboard having size indicators for tracking sequential destination register usage in a multi-threaded processor 有权
标题翻译：记分牌具有用于跟踪多线程处理器中的顺序目的地寄存器使用的大小指示符
公开(公告)号：US08225076B1
公开(公告)日：2012-07-17
申请号：US12233515
申请日：2008-09-18
申请人： Brett W. Coon , Peter C. Mills , Stuart F. Oberman , Ming Y. Siu
发明人： Brett W. Coon , Peter C. Mills , Stuart F. Oberman , Ming Y. Siu
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3838 , G06F9/3879 , G06F9/3885
摘要： A scoreboard memory for a processing unit has separate memory regions allocated to each of the multiple threads to be processed. For each thread, the scoreboard memory stores register identifiers of registers that have pending writes. When an instruction is added to an instruction buffer, the register identifiers of the registers specified in the instruction are compared with the register identifiers stored in the scoreboard memory for that instruction's thread, and a multi-bit value representing the comparison result is generated. The multi-bit value is stored with the instruction in the instruction buffer and may be updated as instructions belonging to the same thread complete their execution. Before the instruction is issued for execution, this multi-bit value is checked. If this multi-bit value indicates that none of the registers specified in the instruction have pending writes, the instruction is allowed to issue for execution.
摘要翻译：用于处理单元的记分板存储器具有分配给要处理的多个线程中的每一个的分离的存储器区域。对于每个线程，记分板存储器存储具有待处理写入的寄存器的寄存器标识符。当指令被添加到指令缓冲器中时，将指令中指定的寄存器的寄存器标识符与存储在该指令的线程的记分板存储器中的寄存器标识进行比较，并生成表示比较结果的多位值。多位值与指令一起存储在指令缓冲器中，并且可以更新为属于同一线程的指令完成其执行。在执行指令之前，将检查该多位值。如果该多位值表示指令中没有指定的寄存器没有挂起写操作，则允许指令执行。

17. 发明授权

US08176265B2 Shared single-access memory with management of multiple parallel requests 有权
标题翻译：具有管理多个并行请求的共享单访问存储器
公开(公告)号：US08176265B2
公开(公告)日：2012-05-08
申请号：US13165638
申请日：2011-06-21
申请人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
发明人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , Y02D10/13
摘要： A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.
摘要翻译：多线程处理器中的并发线程使用内存。任何可寻址的存储位置都可以由任何并发线程访问，但一次只能访问一个位置。存储器耦合到并行处理引擎，其产生一组并行存储器访问请求，每个指定对于不同请求可能相同或不同的目标地址。序列化逻辑选择一个目标地址，并确定哪个请求指定所选择的目标地址。允许所有这些请求并行进行，而其他请求被推迟。可以通过序列化逻辑重新生成和处理延迟请求，以便通过一次访问组中的每个不同的目标地址来满足一组请求。

18. 发明授权

US08108625B1 Shared memory with parallel access and access conflict resolution mechanism 有权
标题翻译：共享内存具有并行访问和访问冲突解决机制
公开(公告)号：US08108625B1
公开(公告)日：2012-01-31
申请号：US11554546
申请日：2006-10-30
申请人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
发明人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
IPC分类号： G06F12/00
CPC分类号： G06F13/1663
摘要： Concurrent threads in a multithreaded processor share access to a memory, with any location in the shared memory being accessible by any thread. In one embodiment, the shared memory has multiple independently-addressable memory banks, and one location per bank can be accessed in parallel. Parallel processing engines executing the threads generate a group of parallel memory access requests. Address conflict logic determines whether the requests can be satisfied in parallel (e.g., based on bank access constraints) and serializes the requests to the extent needed to avoid conflicts. In some embodiments, data read from one address in the shared memory can be broadcast to multiple processing engines.
摘要翻译：多线程处理器中的并发线程共享对内存的访问，任何线程都可以访问共享内存中的任何位置。在一个实施例中，共享存储器具有多个可独立寻址的存储体，并且可以并行地访问每个存储体的一个位置。执行线程的并行处理引擎生成一组并行内存访问请求。地址冲突逻辑确定请求是否可以并行满足（例如，基于银行访问约束），并将请求序列化到避免冲突所需的程度。在一些实施例中，从共享存储器中的一个地址读取的数据可以广播到多个处理引擎。

19. 发明授权

US07484076B1 Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q 有权
标题翻译：执行一次执行Q操作的执行单元上的P操作的SIMD指令（Q
公开(公告)号：US07484076B1
公开(公告)日：2009-01-27
申请号：US11532853
申请日：2006-09-18
申请人： Stuart F. Oberman , Ming Y. Siu , Sameer D. Halepete
发明人： Stuart F. Oberman , Ming Y. Siu , Sameer D. Halepete
IPC分类号： G06F15/80
CPC分类号： G06F9/3869 , G06F9/30105 , G06F9/30109 , G06F9/3012 , G06F9/3836 , G06F9/3851 , G06F9/3875 , G06F9/3887
摘要： Methods, apparatuses, and systems are presented for performing instructions using multiple execution units in a graphics processing unit involving issuing an instruction for P executions of the instruction wherein each execution uses different data, P being a positive integer, the instruction being issued based on a first clock having a first clock rate, operating Q execution units to achieve the P executions of the instruction, Q being a positive integer less than P and greater than one, each of the execution units being operated based on a second clock having a second clock rate higher than the first clock rate of the first clock, and wherein the second clock rate of the second clock is equal to the first clock rate of the first clock multiplied by the ratio P/Q.
摘要翻译：呈现用于在图形处理单元中执行使用多个执行单元的指令的方法，装置和系统，该图形处理单元涉及发出指令的P执行指令，其中每个执行使用不同的数据，P是正整数，基于第一时钟具有第一时钟速率，操作Q执行单元以实现指令的P执行，Q是小于P且大于1的正整数，每个执行单元基于具有第二时钟的第二时钟来操作速率高于第一时钟的第一时钟速率，并且其中第二时钟的第二时钟速率等于第一时钟的第一时钟速率乘以比率P / Q。

20. 发明授权

US07434032B1 Tracking register usage during multithreaded processing using a scoreboard having separate memory regions and storing sequential register size indicators 有权
标题翻译：使用具有独立存储区域的记分板和存储顺序寄存器大小指示符的多线程处理期间跟踪寄存器的使用情况
公开(公告)号：US07434032B1
公开(公告)日：2008-10-07
申请号：US11301589
申请日：2005-12-13
申请人： Brett W. Coon , Peter C. Mills , Stuart F. Oberman , Ming Y. Siu
发明人： Brett W. Coon , Peter C. Mills , Stuart F. Oberman , Ming Y. Siu
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3838 , G06F9/3879 , G06F9/3885
摘要： A scoreboard memory for a processing unit has separate memory regions allocated to each of the multiple threads to be processed. For each thread, the scoreboard memory stores register identifiers of registers that have pending writes. When an instruction is added to an instruction buffer, the register identifiers of the registers specified in the instruction are compared with the register identifiers stored in the scoreboard memory for that instruction's thread, and a multi-bit value representing the comparison result is generated. The multi-bit value is stored with the instruction in the instruction buffer and may be updated as instructions belonging to the same thread complete their execution. Before the instruction is issued for execution, this multi-bit value is checked. If this multi-bit value indicates that none of the registers specified in the instruction have pending writes, the instruction is allowed to issue for execution.
摘要翻译：用于处理单元的记分板存储器具有分配给要处理的多个线程中的每一个的分离的存储器区域。对于每个线程，记分板存储器存储具有待处理写入的寄存器的寄存器标识符。当指令被添加到指令缓冲器中时，将指令中指定的寄存器的寄存器标识符与存储在该指令的线程的记分板存储器中的寄存器标识进行比较，并生成表示比较结果的多位值。多位值与指令一起存储在指令缓冲器中，并且可以更新为属于同一线程的指令完成其执行。在执行指令之前，将检查该多位值。如果该多位值表示指令中没有指定的寄存器没有挂起写操作，则允许指令执行。

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