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11. 发明授权

US07512508B2 Determining and analyzing integrated circuit yield and quality 有权
标题翻译：确定和分析集成电路产量和质量
公开(公告)号：US07512508B2
公开(公告)日：2009-03-31
申请号：US11221395
申请日：2005-09-06
申请人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
发明人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
IPC分类号： G01R31/26 , G06F11/22
CPC分类号： G06F11/2273 , G01R31/01 , G01R31/2846 , G01R31/2853 , G01R31/2894 , G01R31/31704 , G01R31/31835
摘要： Methods, apparatus, and systems for computing and analyzing integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the described methods are also disclosed.
摘要翻译：本文公开了用于计算和分析集成电路产量和质量的方法，装置和系统。例如，在本文公开的一个示例性方法中，从设计用于电子设备中的功能使用的集成电路的处理测试响应接收信息。在该实施例中，该信息表示在集成电路测试期间观察到的集成电路故障以及导致集成电路故障的可能的产量限制因素。通过统计分析接收的信息来确定集成电路中的一个或多个可能的屈服限制因素实际引起集成电路故障的概率。报告了一个或多个可能的屈服限制因素实际上导致集成电路故障的概率。还公开了包括用于使计算机执行任何所述方法的计算机可执行指令的有形计算机可读介质。

12. 发明授权

US07437636B2 Method and apparatus for at-speed testing of digital circuits 有权
标题翻译：用于数字电路高速测试的方法和装置
公开(公告)号：US07437636B2
公开(公告)日：2008-10-14
申请号：US11265488
申请日：2005-11-01
申请人： Janusz Rajski , Abu Hassan , Robert Thompson , Nagesh Tamarapalli
发明人： Janusz Rajski , Abu Hassan , Robert Thompson , Nagesh Tamarapalli
IPC分类号： G01R31/28 , G06F11/00 , G06F1/04
CPC分类号： G01R31/318594 , G01R31/31858
摘要： Exemplary schemes for multi-frequency at-speed logic Built-In Self Test (BIST) are provided. For example, certain schemes allow at-speed testing of very high frequency integrated circuits controlled by a clock signal generated externally or on-chip. Some of the disclosed schemes are also applicable to testing of circuits with multiple clock domains which can be either the same frequency or different frequency. In particular embodiments, the loading and unloading of scan chains is separated from the at-speed testing of the logic between the respective domains and may be done at a faster or slower frequency than the at-speed testing. In certain embodiments, only the capture cycle is performed at the corresponding system timing. In some embodiments, a programmable capture window makes it possible to test every intra- and inter-domain at-speed without the negative impact of clock skew between clock domains.
摘要翻译：提供了多频率高速逻辑内置自检（BIST）的示范方案。例如，某些方案允许对由外部或片上产生的时钟信号控制的非常高频率的集成电路进行高速测试。所公开的方案中的一些也适用于具有可以是相同频率或不同频率的多个时钟域的电路的测试。在特定实施例中，扫描链的加载和卸载与各个域之间的逻辑的速度测试分离，并且可以以比速度测试更快或更慢的频率进行。在某些实施例中，在对应的系统定时仅执行捕获周期。在一些实施例中，可编程捕获窗口使得可以在时钟域之间没有时钟偏移的负面影响的情况下测试每个域内和域间的速度。

13. 发明申请

US20060066339A1 Determining and analyzing integrated circuit yield and quality 有权
标题翻译：确定和分析集成电路产量和质量
公开(公告)号：US20060066339A1
公开(公告)日：2006-03-30
申请号：US11221395
申请日：2005-09-06
申请人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
发明人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
IPC分类号： G01R31/26
CPC分类号： G06F11/2273 , G01R31/01 , G01R31/2846 , G01R31/2853 , G01R31/2894 , G01R31/31704 , G01R31/31835
摘要： Methods, apparatus, and systems for computing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein, information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the described methods are also disclosed.
摘要翻译：本文公开了用于计算，分析和改进集成电路产量和质量的方法，装置和系统。例如，在本文公开的一个示例性方法中，从设计用于电子设备中的功能使用的集成电路的处理测试响应中接收信息。在该实施例中，该信息表示在集成电路测试期间观察到的集成电路故障以及导致集成电路故障的可能的产量限制因素。通过统计分析接收的信息来确定集成电路中的一个或多个可能的屈服限制因素实际上引起集成电路故障的概率。报告了一个或多个可能的屈服限制因素实际上导致集成电路故障的概率。还公开了包括用于使计算机执行任何所述方法的计算机可执行指令的有形计算机可读介质。

14. 发明申请

US20060053357A1 Integrated circuit yield and quality analysis methods and systems 审中-公开
标题翻译：集成电路产量和质量分析方法和系统
公开(公告)号：US20060053357A1
公开(公告)日：2006-03-09
申请号：US11221373
申请日：2005-09-06
申请人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
发明人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/2273 , G01R31/01 , G01R31/2846 , G01R31/2853 , G01R31/2894 , G01R31/31704 , G01R31/31835
摘要： Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, design defect extraction rules are derived at least partially from a set of design manufacturing rules. Potential defects are extracted from a representation of an integrated circuit layout using the design defect extraction rules. Circuit test stimuli applied during one or more circuit tests are determined. Test responses resulting from the applied circuit tests are evaluated to identify integrated circuits that fail and to identify the occurrence in the failing integrated circuits of one or more potential types of defects associated with the applied circuit tests. Information concerning the repetitive identification in the failing integrated circuits of the occurrence of potential types of defects is collected and analyzed to determine the likelihood of potential types of defects being present in integrated circuits manufactured in accordance with the layout.
摘要翻译：本文公开了用于测试，分析和提高集成电路产量和质量的方法，装置和系统。例如，在一个示例性实施例中，至少部分地从一组设计制造规则导出设计缺陷提取规则。使用设计缺陷提取规则从集成电路布局的表示中提取潜在缺陷。确定在一个或多个电路测试期间施加的电路测试刺激。评估由应用电路测试产生的测试响应，以识别故障的集成电路，并识别故障集成电路中与应用电路测试相关的一种或多种潜在类型的缺陷的发生。收集和分析关于发生潜在类型缺陷的故障集成电路中的重复识别的信息，以确定存在于根据布局制造的集成电路中的潜在类型的缺陷的可能性。

15. 发明授权

US07987442B2 Fault dictionaries for integrated circuit yield and quality analysis methods and systems 有权
标题翻译：集成电路产品和质量分析方法和系统的故障字典
公开(公告)号：US07987442B2
公开(公告)日：2011-07-26
申请号：US11221394
申请日：2005-09-06
申请人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
发明人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
IPC分类号： G06F17/50 , G06F9/455 , G06F11/00
CPC分类号： G06F11/2273 , G01R31/01 , G01R31/2846 , G01R31/2853 , G01R31/2894 , G01R31/31704 , G01R31/31835
摘要： Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, one or more fault dictionaries are generated for identifying one or more defect candidates from corresponding observation point combinations. In this exemplary method, the observation point combinations indicate the observation points of a circuit-under-test that captured faulty test values upon application of a respective test pattern. Further, the one or more fault dictionaries in one embodiment are generated by: (a) for a first defect candidate, storing one or more first indicators indicative of test patterns detecting the first defect candidate, and (b) for a second defect candidate, storing at least a second indicator indicative of the test patterns that detect the second defect candidate, the second indicator comprising a bit mask that indicates which of the test patterns detecting the first defect candidate also detect the second defect candidate.
摘要翻译：本文公开了用于测试，分析和提高集成电路产量和质量的方法，装置和系统。例如，在一个示例性实施例中，生成用于从相应的观察点组合识别一个或多个缺陷候选的一个或多个故障字典。在该示例性方法中，观察点组合表示在应用相应测试图案时捕获故障测试值的被测电路的观察点。此外，一个实施例中的一个或多个故障字典通过以下方式产生：（a）对于第一缺陷候选，存储指示检测第一缺陷候选的测试图案的一个或多个第一指示符，以及（b）对于第二缺陷候选，存储指示检测第二缺陷候选的测试图案的至少第二指示符，第二指示符包括指示检测第一缺陷候选的哪个测试图案还检测第二缺陷候选的位掩码。

16. 发明授权

US07805651B2 Phase shifter with reduced linear dependency 有权
标题翻译：移相器具有减少的线性依赖性
公开(公告)号：US07805651B2
公开(公告)日：2010-09-28
申请号：US12633601
申请日：2009-12-08
申请人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
发明人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/31813 , G01R31/318385 , G01R31/318547 , G01R31/318594
摘要： A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.
摘要翻译：公开了用于自动合成移相器的方法，该移相器用于消除驱动并行扫描链的伪随机测试图形发生器所特征的结构依赖性的影响。使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。

17. 发明申请

US20090210183A1 DETERMINING AND ANALYZING INTEGRATED CIRCUIT YIELD AND QUALITY 审中-公开
标题翻译：确定和分析集成电路的质量和质量
公开(公告)号：US20090210183A1
公开(公告)日：2009-08-20
申请号：US12415806
申请日：2009-03-31
申请人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
发明人： Janusz Rajski , Gang Chen , Martin Keim , Nagesh Tamarapalli , Manish Sharma , Huaxing Tang
IPC分类号： G06F19/00
CPC分类号： G06F11/2273 , G01R31/01 , G01R31/2846 , G01R31/2853 , G01R31/2894 , G01R31/31704 , G01R31/31835
摘要： Methods, apparatus, and systems for computing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein, information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the described methods are also disclosed.
摘要翻译：本文公开了用于计算，分析和改进集成电路产量和质量的方法，装置和系统。例如，在本文公开的一个示例性方法中，从设计用于电子设备中的功能使用的集成电路的处理测试响应中接收信息。在该实施例中，该信息表示在集成电路测试期间观察到的集成电路故障以及导致集成电路故障的可能的产量限制因素。通过统计分析接收的信息来确定集成电路中的一个或多个可能的屈服限制因素实际上引起集成电路故障的概率。报告了一个或多个可能的屈服限制因素实际上导致集成电路故障的概率。还公开了包括用于使计算机执行任何所述方法的计算机可执行指令的有形计算机可读介质。

18. 发明授权

US6070261A Multi-phase test point insertion for built-in self test of integrated circuits 失效
标题翻译：集成电路内置自检的多相测试点插入
公开(公告)号：US6070261A
公开(公告)日：2000-05-30
申请号：US24962
申请日：1998-02-11
申请人： Nagesh Tamarapalli , Janusz Rajski
发明人： Nagesh Tamarapalli , Janusz Rajski
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/263 , G01R31/318342 , G06F17/5022 , G06F2217/14
摘要： Method and apparatus for providing high quality Built-In-Self-Test (BIST) of integrated circuits, while guaranteeing convergence and reducing area-overhead and power dissipation during test mode. A divide and conquer approach is used to partition the test into multiple phases during which a number of test patterns are applied to a circuit under test (CUT). The design of each phase (the selection of control and observation points) is guided by a progressively reduced list of undetected faults. Within a phase, a set of control points maximally contributing to the fault coverage achieved so far is identified using a unique probabilistic fault simulation (PFS) technique. The PFS technique accurately computes a propagation profile of the circuit and uses it to determine the impact of a new control point in the presence of control points selected so far. In this manner, in each new phase a group of control points, driven by fixed values and operating synergistically, is enabled. Observation points are selected in a similar fashion to further enhance the fault coverage. The sets of control and observation points are then inserted into the circuit under test and a new, reduced list of undetected faults is determined through exact fault simulation. This process is iterative and continues until the number of undetected faults is less than or equal to an acceptable threshold, a pre-specified number of control and observation points have been inserted, or the maximum number of specified test phases has been reached.
摘要翻译：提供集成电路的高质量内置自检（BIST）的方法和装置，同时保证在测试模式下的融合并减少面积开销和功耗。分割和征服方法用于将测试分成多个阶段，在此阶段将多个测试模式应用于被测电路（CUT）。每个阶段的设计（控制和观测点的选择）都是逐渐减少的未检测到的故障列表。在一个阶段中，使用独特的概率故障模拟（PFS）技术来识别到目前为止所达到的最大限度地有助于故障覆盖的一组控制点。 PFS技术准确地计算电路的传播特性，并使用它来确定在目前为止选择的控制点存在时新控制点的影响。以这种方式，在每个新阶段，启用由固定值驱动并且协同操作的一组控制点。以类似的方式选择观测点，以进一步增强故障覆盖。然后将控制和观测点的集合插入到被测电路中，并通过精确的故障模拟确定未被检测的故障的新的减少的列表。该过程是迭代的，并且持续到未检测到的故障的数量小于或等于可接受的阈值，已经插入了预定数量的控制和观察点，或者达到了指定的测试阶段的最大数目。

19. 发明申请

US20100083063A1 PHASE SHIFTER WITH REDUCED LINEAR DEPENDENCY 有权
标题翻译：具有减少线性关系的相位变换器
公开(公告)号：US20100083063A1
公开(公告)日：2010-04-01
申请号：US12633601
申请日：2009-12-08
申请人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
发明人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318541 , G01R31/31813 , G01R31/318385 , G01R31/318547 , G01R31/318594
摘要： A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.
摘要翻译：公开了用于自动合成移相器的方法，该移相器用于消除驱动并行扫描链的伪随机测试图形发生器所特征的结构依赖性的影响。使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。

20. 发明申请

US20090187800A1 PHASE SHIFTER WITH REDUCED LINEAR DEPENDENCY 有权
标题翻译：具有减少线性关系的相位变换器
公开(公告)号：US20090187800A1
公开(公告)日：2009-07-23
申请号：US12412267
申请日：2009-03-26
申请人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
发明人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318541 , G01R31/31813 , G01R31/318385 , G01R31/318547 , G01R31/318594
摘要： A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.
摘要翻译：公开了用于自动合成移相器的方法，该移相器用于消除驱动并行扫描链的伪随机测试图形发生器所特征的结构依赖性的影响。使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。

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