专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08749289B2 Multi-phase clock generation apparatus and method 有权
标题翻译：多相时钟发生装置及方法
公开(公告)号：US08749289B2
公开(公告)日：2014-06-10
申请号：US13330648
申请日：2011-12-19
申请人： Shenggao Li , Roan M. Nicholson
发明人： Shenggao Li , Roan M. Nicholson
IPC分类号： H03K27/00
CPC分类号： H03K5/15013 , G06F1/06 , H03B5/364
摘要： A multi-phase clock generator may receive an input clock signal as an input. The clock generator may also receive an inverse of the input clock signal. The clock generator may produce a plurality of output clock signals having different phases. The phases of the output clock signals may be evenly spaced. The output clock signals may have a similar waveform to the input clock signal, with a frequency that is lower than the input clock signal by a division factor.
摘要翻译：多相时钟发生器可以接收输入时钟信号作为输入。时钟发生器也可以接收输入时钟信号的反相。时钟发生器可以产生具有不同相位的多个输出时钟信号。输出时钟信号的相位可以均匀间隔。输出时钟信号可能具有与输入时钟信号相似的波形，其频率低于输入时钟信号的分频因子。

12. 发明授权

US06853254B2 Anti-deadlock circuit and method for phase-locked loops 失效
标题翻译：防死锁电路和锁相环的方法
公开(公告)号：US06853254B2
公开(公告)日：2005-02-08
申请号：US10330559
申请日：2002-12-30
申请人： Shenggao Li
发明人： Shenggao Li
IPC分类号： H03B5/32 , H03L7/00 , H03L7/089 , H03L7/10 , H03L7/18
CPC分类号： H03L7/18 , H03L7/0896 , H03L7/0898 , H03L7/10 , H03L7/105
摘要： A system and method for controlling a phase-locked loop detects a deadlock condition and then adjusts an output frequency of an oscillator until the deadlock condition is corrected. The deadlock condition may be detected based on a value of a charge pump signal which controls the oscillator frequency. In accordance with one embodiment, deadlock is detected if the value of the charge pump signal approaches one of two supply rail voltages. The deadlock condition is overcome by manipulating current signals output from the charge pump. This is accomplished by turning off the current from one charge-pump current source and increasing current from a second-charge pump current source. The increased current may be provided by a third current source located within or external to the charge pump. By adding current from the third current source, the output frequency of the phase-locked loop will be driven lower until a value is reached which effectively pulls the PLL out of the deadlock condition.
摘要翻译：用于控制锁相环的系统和方法检测死锁状况，然后调整振荡器的输出频率直到纠正死锁状态。可以基于控制振荡器频率的电荷泵信号的值来检测死锁状态。根据一个实施例，如果电荷泵信号的值接近两个电源电压之一，则检测到死锁。通过操纵从电荷泵输出的电流信号来克服死锁状况。这是通过关闭来自一个电荷泵电流源的电流和从第二电荷泵电流源增加电流来实现的。增加的电流可以由位于电荷泵内部或外部的第三电流源提供。通过从第三个电流源添加电流，锁相环的输出频率将被驱动较低，直到达到有效地将PLL从死锁状态拉出的值。

13. 发明授权

US08981822B2 High speed dual modulus divider 有权
标题翻译：高速双模分频器
公开(公告)号：US08981822B2
公开(公告)日：2015-03-17
申请号：US13619090
申请日：2012-09-14
申请人： Shenggao Li
发明人： Shenggao Li
IPC分类号： H03B19/00 , H03K21/02 , H03K23/68
CPC分类号： H03K21/023 , H03K23/68
摘要： Described is an apparatus comprising a plurality of logic units arranged in a ring, wherein an output terminal of each logic unit from the plurality of logic units is coupled to an input terminal of a next logic unit from the plurality of logic units, wherein the plurality of logic units includes a first multiple input logic unit having input nodes coupled to at least two output terminals of logic units from the plurality of logic units; and a plurality of latch units coupled to the output terminals of the plurality of logic units.
摘要翻译：描述了一种包括布置在环中的多个逻辑单元的装置，其中来自多个逻辑单元的每个逻辑单元的输出端从多个逻辑单元耦合到下一逻辑单元的输入端，其中多个逻辑单元包括具有耦合到来自多个逻辑单元的逻辑单元的至少两个输出端的输入节点的第一多输入逻辑单元; 以及耦合到所述多个逻辑单元的输出端的多个锁存单元。

14. 发明申请

US20140079177A1 HIGH SPEED DUAL MODULUS DIVIDER 有权
标题翻译：高速双模块分路器
公开(公告)号：US20140079177A1
公开(公告)日：2014-03-20
申请号：US13619090
申请日：2012-09-14
申请人： Shenggao Li
发明人： Shenggao Li
IPC分类号： H03K23/40 , H03K3/037
CPC分类号： H03K21/023 , H03K23/68
摘要： Described is an apparatus comprising a plurality of logic units arranged in a ring, wherein an output terminal of each logic unit from the plurality of logic units is coupled to an input terminal of a next logic unit from the plurality of logic units, wherein the plurality of logic units includes a first multiple input logic unit having input nodes coupled to at least two output terminals of logic units from the plurality of logic units; and a plurality of latch units coupled to the output terminals of the plurality of logic units.
摘要翻译：描述了一种包括布置在环中的多个逻辑单元的装置，其中来自多个逻辑单元的每个逻辑单元的输出端从多个逻辑单元耦合到下一逻辑单元的输入端，其中多个逻辑单元包括具有耦合到来自多个逻辑单元的逻辑单元的至少两个输出端的输入节点的第一多输入逻辑单元; 以及耦合到所述多个逻辑单元的输出端的多个锁存单元。

15. 发明授权

US07421052B2 Oscillator frequency selection 有权
标题翻译：振荡频率选择
公开(公告)号：US07421052B2
公开(公告)日：2008-09-02
申请号：US11139809
申请日：2005-05-27
申请人： Shenggao Li
发明人： Shenggao Li
IPC分类号： H03D3/24 , H03D3/18
CPC分类号： H03B27/00 , H03B5/1209 , H03B5/1215 , H03B5/1225 , H03B5/1228 , H03B5/1265 , H03B5/1271 , H03B2200/005 , H03B2200/0078
摘要： According to some embodiments, a frequency adjuster adjusts a frequency of an oscillator. For example, the frequency adjuster might include a plurality of capacitors that are selectable using a digital control signal, and selection logic may adjust the digital control signal based on a received indication associated with the oscillator's frequency.
摘要翻译：根据一些实施例，频率调节器调节振荡器的频率。例如，频率调节器可以包括使用数字控制信号可选择的多个电容器，并且选择逻辑可以基于与振荡器频率相关联的接收指示来调整数字控制信号。

16. 发明申请

US20070009267A1 Driving a laser using an electrical link driver 审中-公开
标题翻译：使用电气连接驱动器驱动激光
公开(公告)号：US20070009267A1
公开(公告)日：2007-01-11
申请号：US11165298
申请日：2005-06-22
申请人： Darren Crews , Shenggao Li , Chien-Chang Liu , Robert Johnston
发明人： Darren Crews , Shenggao Li , Chien-Chang Liu , Robert Johnston
IPC分类号： H04B10/04
CPC分类号： H04B10/504
摘要： An electrical link driver for a point-to-point link is coupled to a laser. The electrical link driver provides a modulation current to the laser.
摘要翻译：用于点对点链路的电连接驱动器耦合到激光器。电连接驱动器向激光器提供调制电流。

17. 发明申请

US20060269014A1 Oscillator frequency selection 有权
标题翻译：振荡频率选择
公开(公告)号：US20060269014A1
公开(公告)日：2006-11-30
申请号：US11139809
申请日：2005-05-27
申请人： Shenggao Li
发明人： Shenggao Li
IPC分类号： H03D3/24
CPC分类号： H03B27/00 , H03B5/1209 , H03B5/1215 , H03B5/1225 , H03B5/1228 , H03B5/1265 , H03B5/1271 , H03B2200/005 , H03B2200/0078
摘要： According to some embodiments, a frequency adjuster adjusts a frequency of an oscillator. For example, the frequency adjuster might include a plurality of capacitors that are selectable using a digital control signal, and selection logic may adjust the digital control signal based on a received indication associated with the oscillator's frequency.
摘要翻译：根据一些实施例，频率调节器调节振荡器的频率。例如，频率调节器可以包括使用数字控制信号可选择的多个电容器，并且选择逻辑可以基于与振荡器频率相关联的接收指示来调整数字控制信号。

18. 发明授权

US06954110B2 Replica cell for ring oscillator 失效
公开(公告)号：US06954110B2
公开(公告)日：2005-10-11
申请号：US10648919
申请日：2003-08-27
申请人： Shenggao Li
发明人： Shenggao Li
IPC分类号： H03K3/011 , H03K3/03 , H03L7/07 , H03L7/099 , H03L7/00
CPC分类号： H03K3/0322 , H03K3/011 , H03L7/07 , H03L7/0995
摘要： In some embodiments, a ring oscillator includes a plurality of delay cells coupled in series as a ring, and a replica cell coupled to the delay cells to provide at least one bias signal to the delay cells. The replica cell includes a differential transistor pair formed of a first transistor and a second transistor. The first transistor has a drain terminal and a gate terminal coupled to the drain terminal. The second transistor has a drain terminal and a gate terminal coupled to the drain terminal of the second transistor.

19. 发明授权

US08520428B2 Combined data level-shifter and DE-skewer 有权
标题翻译：组合数据电平转换器和DE串
公开(公告)号：US08520428B2
公开(公告)日：2013-08-27
申请号：US13072375
申请日：2011-03-25
申请人： Edward E. Helder , Brandon M. Walters , Mahesh M. Chheda , Shenggao Li , Kenneth R. Smits
发明人： Edward E. Helder , Brandon M. Walters , Mahesh M. Chheda , Shenggao Li , Kenneth R. Smits
IPC分类号： G11C11/00
CPC分类号： H03K19/018521 , G11C7/1057 , G11C7/1066
摘要： Various embodiments of this disclosure may describe a circuit for transmitting data from a transmitting region of an integrated circuit to a receiving region of the integrated circuit. The circuit may level-shift the data to the appropriate voltage level and may have good tolerance to clock skews. Other embodiments, including an integrated circuit having the circuit or a system with the integrated circuit, may also be disclosed or claimed.
摘要翻译：本公开的各种实施例可以描述用于将数据从集成电路的发送区域发送到集成电路的接收区域的电路。电路可能会将数据电平移位到适当的电压电平，并且可能对时钟偏移具有良好的容限。包括具有该电路的集成电路或具有集成电路的系统的其它实施例也可以被公开或要求保护。

20. 发明申请

US20130154691A1 MULTI-PHASE CLOCK GENERATION APPARATUS AND METHOD 有权
标题翻译：多相时钟发生装置及方法
公开(公告)号：US20130154691A1
公开(公告)日：2013-06-20
申请号：US13330648
申请日：2011-12-19
申请人： Shenggao Li , Roan M. Nicholson
发明人： Shenggao Li , Roan M. Nicholson
IPC分类号： H03H11/16 , H03B19/00
CPC分类号： H03K5/15013 , G06F1/06 , H03B5/364
摘要： A multi-phase clock generator may receive an input clock signal as an input. The clock generator may also receive an inverse of the input clock signal. The clock generator may produce a plurality of output clock signals having different phases. The phases of the output clock signals may be evenly spaced. The output clock signals may have a similar waveform to the input clock signal, with a frequency that is lower than the input clock signal by a division factor.
摘要翻译：多相时钟发生器可以接收输入时钟信号作为输入。时钟发生器也可以接收输入时钟信号的反相。时钟发生器可以产生具有不同相位的多个输出时钟信号。输出时钟信号的相位可以均匀间隔。输出时钟信号可能具有与输入时钟信号相似的波形，其频率低于输入时钟信号的分频因子。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式