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11. 发明授权

US07386732B2 Integrated system security method 失效
标题翻译：集成系统安全方法
公开(公告)号：US07386732B2
公开(公告)日：2008-06-10
申请号：US11381436
申请日：2006-05-03
申请人： Edward E. Kelley , Franco Motika , Paul V. Motika , Eric M. Motika
发明人： Edward E. Kelley , Franco Motika , Paul V. Motika , Eric M. Motika
IPC分类号： H04K1/00 , H04L9/00
CPC分类号： G06F21/88 , G06F21/31 , G07C9/00142
摘要： Logic scan based design and electronic fuse (e-fuse) technology are combined to create a circuit macro function that is integrated in a non-critical area of a processor chip or related circuit to provide a new means of securing electronic systems and devices such as computers, appliances, consumer electronics, automobiles, etc. from theft or unauthorized use. Level sensitive scan design (LSSD) techniques are used in conjunction with e-fuses to inhibit or enable system components and sub-components based upon a pre-initialized configuration which must be enabled by a user via password entry.
摘要翻译：基于逻辑扫描的设计和电子熔丝（e-fuse）技术被组合以产生集成在处理器芯片或相关电路的非关键区域中的电路宏功能，以提供保护电子系统和设备的新手段，例如计算机，电器，消费电子，汽车等从盗窃或未经授权的使用。等级敏感扫描设计（LSSD）技术与电子熔丝一起使用，以根据用户通过密码输入启用的预初始化配置来禁止或启用系统组件和子组件。

12. 发明申请

US20080059857A1 METHODS AND APPARATUS FOR TESTING A SCAN CHAIN TO ISOLATE DEFECTS 失效
标题翻译：用于测试扫描链以分离缺陷的方法和装置
公开(公告)号：US20080059857A1
公开(公告)日：2008-03-06
申请号：US11924597
申请日：2007-10-25
申请人： LEENDERT HUISMAN , William Huott , Maroun Kassab , Franco Motika
发明人： LEENDERT HUISMAN , William Huott , Maroun Kassab , Franco Motika
IPC分类号： G01R31/28
CPC分类号： G01R31/318533
摘要： Systems, methods and apparatus are provided for isolating a defect in a scan chain. The invention includes modifying a first test mode of a plurality of latches included in a scan chain, operating the latches in the modified first test mode, and operating the plurality of latches included in the scan chain in a second test mode. A portion of the scan chain adjacent and following a stuck-@-0 or stuck-@-1 fault in the scan chain may store and/or output a value complementary to the value on the output of the previous portion of the scan chain due to the fault. Such values may be unloaded from the scan chain and used for diagnosing (e.g., isolating a defect in) the defective scan chain. Numerous other aspects are provided.
摘要翻译：提供了用于隔离扫描链中的缺陷的系统，方法和装置。本发明包括修改包括在扫描链中的多个锁存器的第一测试模式，在修改的第一测试模式下操作锁存器，以及在第二测试模式下操作包括在扫描链中的多个锁存器。扫描链中与扫描链相邻并跟随卡纸 - @ - 0或卡住 - - - 1故障的部分扫描链可以存储和/或输出与扫描链的先前部分的输出值相匹配的值，到了错误。这些值可以从扫描链中卸载并用于诊断（例如，分离缺陷）缺陷扫描链。提供了许多其他方面。

13. 发明申请

US20080036486A1 INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION 失效
公开(公告)号：US20080036486A1
公开(公告)日：2008-02-14
申请号：US11876066
申请日：2007-10-22
申请人： Anne Gattiker , David Grosch , Marc Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul Zuchowski
发明人： Anne Gattiker , David Grosch , Marc Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/3008 , G01R31/31858
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

14. 发明授权

US07128273B2 Secure credit card adapter 有权
标题翻译：安全的信用卡适配器
公开(公告)号：US07128273B2
公开(公告)日：2006-10-31
申请号：US10907207
申请日：2005-03-24
申请人： Edward E. Kelley , Franco Motika , Kim H. Ruffing
发明人： Edward E. Kelley , Franco Motika , Kim H. Ruffing
IPC分类号： G06K19/06 , G06K7/00
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/382 , G07F7/0886
摘要： A secure card adapter provides for writing of highly secure, single transaction information on a machine-readable medium of a card structure in accordance with a format that may be downloaded from an external data source. The card structure may be, for example, an existing access authorization card or an existing credit card containing account-specific information which can be read and stored in memory of the secure card adapter. Once such account-specific information is read from an existing access authorization or credit card, secure transaction information can be written, together with the account specific information in accordance with the downloaded format information on another card structure to provide a universal access authorization and/or credit card. Thus the secure card adapter provides an enhanced degree of security through an existing or transitional communication infrastructure.
摘要翻译：安全卡适配器提供根据可从外部数据源下载的格式在卡结构的机器可读介质上写入高度安全的单个交易信息。卡结构可以是例如现有的访问授权卡或包含可被读取并存储在安全卡适配器的存储器中的特定于特定信息的现有信用卡。一旦从现有的访问授权或信用卡读取这样的特定于特定信息的信息，可以根据下载的关于另一个卡结构的格式信息，将帐户特定信息与安全交易信息一起写入以提供通用访问授权和/或信用卡。因此，安全卡适配器通过现有或过渡的通信基础设施提供增强的安全性。

15. 发明申请

US20060200410A1 SECURE CELL PHONE FOR ATM TRANSACTIONS 有权
标题翻译：安全电话用于ATM交易
公开(公告)号：US20060200410A1
公开(公告)日：2006-09-07
申请号：US10906690
申请日：2005-03-02
申请人： Edward Kelley , Franco Motika
发明人： Edward Kelley , Franco Motika
IPC分类号： G06Q40/00 , G07F19/00 , G07D11/00
CPC分类号： G07F19/20 , G06Q20/1085 , G06Q20/32 , G06Q20/4014
摘要： A method, secure cell phone and system for securely accessing an automated banking machine using such secure cell phone. The secure cell phone includes a read only memory device in combination with two linear feedback shift registers for generating a unique security transaction code, which includes a cell phone identification concatenated with two pseudo random codes. The automated banking machine is called from the cell phone. One of the pseudo random codes is input into a software emulation of the cell phone circuitry running on the automated banking machine to generate a computed pseudo random code. This computed code is concatenated the input pseudo random code and a determined cell phone identification to generate a computed transaction code. The automated banking machine is securely accessed using the secure cell phone if the computed transaction code matches the unique security transaction code.
摘要翻译：一种使用这种安全手机安全访问自动银行机的安全手机和系统的方法。安全手机包括与两个线性反馈移位寄存器组合的只读存储器装置，用于产生唯一的安全事务代码，其包括与两个伪随机代码连接的蜂窝电话标识符。自动银行机从手机呼叫。将伪随机码中的一个输入到在自动银行机上运行的蜂窝电话线路的软件仿真，以生成计算的伪随机码。该计算的代码将输入的伪随机码和确定的蜂窝电话标识相连，以产生计算的交易代码。如果计算的交易代码与唯一的安全交易代码相匹配，则使用安全手机安全地访问自动银行机。

16. 发明申请

US20060168455A1 SECURE COMPUTER PASSWORD SYSTEM AND METHOD 失效
标题翻译：安全计算机密码系统和方法
公开(公告)号：US20060168455A1
公开(公告)日：2006-07-27
申请号：US10905854
申请日：2005-01-24
申请人： Edward Kelley , Franco Motika , Tijs Wilbrink
发明人： Edward Kelley , Franco Motika , Tijs Wilbrink
IPC分类号： H04L9/00
CPC分类号： G06F21/31 , G06F21/6209 , H04L9/3226
摘要： An enhanced security method is provided for accessing information from a second computer using a password at a first computer. According to such method, a password used for accessing information is inputted to the first computer and stored on the first computer. Thereafter, the stored password is encoded using an encoding algorithm which is system specific to the first computer, and the encoded password is then transmitted to the second computer. The encoded password is used at the second computer to grant or deny access to the requested information, without the second computer having to decode the encoded password to obtain the password stored on the first computer.
摘要翻译：提供了增强的安全方法，用于在第一计算机处使用密码从第二计算机访问信息。根据这种方法，将用于访问信息的密码输入到第一计算机并存储在第一计算机上。此后，使用系统特定于第一计算机的编码算法对存储的密码进行编码，然后将经编码的密码发送到第二计算机。编码的密码在第二计算机上用于授予或拒绝对所请求的信息的访问，而第二计算机必须对编码密码进行解码以获得存储在第一计算机上的密码。

17. 发明授权

US07076663B2 Integrated system security method 失效
公开(公告)号：US07076663B2
公开(公告)日：2006-07-11
申请号：US09992893
申请日：2001-11-06
申请人： Edward E. Kelley , Franco Motika , Paul V. Motika , Eric M. Motika
发明人： Edward E. Kelley , Franco Motika , Paul V. Motika , Eric M. Motika
IPC分类号： H04K1/00 , H04L9/00
CPC分类号： G06F21/88 , G06F21/31 , G07C9/00142
摘要： Logic scan based design and electronic fuse (e-fuse) technology are combined to create a circuit macro function that is integrated in a non-critical area of a processor chip or related circuit to provide a new means of securing electronic systems and devices such as computers, appliances, consumer electronics, automobiles, etc. from theft or unauthorized use. Level sensitive scan design (LSSD) techniques are used in conjunction with e-fuses to inhibit or enable system components and sub-components based upon a pre-initialized configuration which must be enabled by a user via password entry.

18. 发明申请

US20060071653A1 Integrated circuit testing methods using well bias modification 失效
标题翻译：集成电路测试方法采用偏置修正
公开(公告)号：US20060071653A1
公开(公告)日：2006-04-06
申请号：US10539247
申请日：2003-02-20
申请人： Anne Gattiker , David Grosch , Marc Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul Zuchowski
发明人： Anne Gattiker , David Grosch , Marc Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul Zuchowski
IPC分类号： G01R19/00
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/2856 , G01R31/3004 , G01R31/3008
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.
摘要翻译：测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。此外，这些方法在应力测试期间提供更有效的应力。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

19. 发明授权

US07017095B2 Functional pattern logic diagnostic method 失效
标题翻译：功能模式逻辑诊断方法
公开(公告)号：US07017095B2
公开(公告)日：2006-03-21
申请号：US10064398
申请日：2002-07-10
申请人： Donato Forlenza , Franco Motika , Phillip J. Nigh
发明人： Donato Forlenza , Franco Motika , Phillip J. Nigh
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318586 , G01R31/318544
摘要： A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on the functional failure by determining the location of and type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.
摘要翻译：通过组合确定性和功能测试，通过确定故障电路中的错误的位置和类型，基于功能故障来创建新的测试模式来诊断半导体器件功能测试故障的方法。这是通过在功能测试期间识别故障向量来实现的，通过在故障向量之前从LSSD扫描链中卸载锁存器的值来观察故障设备的状态，从锁存器的未加载状态生成LOAD，应用生成LOAD作为新创建的独立LSSD确定性模式的第一个事件，将产生故障的主输入和时钟应用于正确操作的设备，卸载正确操作设备的输出以生成确定性LSSD模式; 以及将生成的确定性LSSD模式应用于故障设备，以使用现有的LSSD确定性工具来诊断故障。

20. 发明授权

US07007380B2 TFI probe I/O wrap test method 失效
标题翻译： TFI探针I / O包装测试方法
公开(公告)号：US07007380B2
公开(公告)日：2006-03-07
申请号：US10707926
申请日：2004-01-26
申请人： Gobinda Das , Franco Motika
发明人： Gobinda Das , Franco Motika
IPC分类号： H01K3/10
CPC分类号： H01L22/34 , G01R31/318536 , G01R31/318558 , G01R31/318563 , G01R31/318572 , Y10T29/49117 , Y10T29/49155 , Y10T29/49165 , Y10T29/49764
摘要： A method for testing external connections to semiconductor devices. The method includes providing an external electrical path between selected external connections on the semiconductor devices.
摘要翻译：一种用于测试与半导体器件的外部连接的方法。该方法包括在半导体器件上的选定外部连接之间提供外部电路径。

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