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11. 发明授权

US07466171B2 Voltage detection circuit and circuit for generating a trigger flag signal 失效
标题翻译：用于产生触发标志信号的电压检测电路和电路
公开(公告)号：US07466171B2
公开(公告)日：2008-12-16
申请号：US11623119
申请日：2007-01-15
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
IPC分类号： H03L7/00
CPC分类号： H03K5/153
摘要： An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.
摘要翻译：一种集成电路，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

12. 发明申请

US20080169844A1 Voltage Detection Circuit In An Integrated Circuit And Method Of Generating A Trigger Flag Signal 失效
标题翻译：集成电路中的电压检测电路和产生触发标志信号的方法
公开(公告)号：US20080169844A1
公开(公告)日：2008-07-17
申请号：US11623119
申请日：2007-01-15
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
IPC分类号： H03K5/153
CPC分类号： H03K5/153
摘要： An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.
摘要翻译：一种集成电路，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

13. 发明申请

US20090179670A1 PERFORMANCE INVERSION DETECTION CIRCUIT AND A DESIGN STRUCTURE FOR THE SAME 审中-公开
标题翻译：性能反相检测电路及其设计结构
公开(公告)号：US20090179670A1
公开(公告)日：2009-07-16
申请号：US12014430
申请日：2008-01-15
申请人： Albert M. Chu , John A. Fifield , Daryl M. Seitzer , Hongfei Wu
发明人： Albert M. Chu , John A. Fifield , Daryl M. Seitzer , Hongfei Wu
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F2200/447 , H03F2203/45586 , H03F2203/45618 , H03F2203/45622
摘要： A circuit containing a parallel connection of a first sub-circuit and a second sub-circuit is provided. The first sub-circuit comprises a serial connection of a first field effect transistor having a first threshold voltage and a first voltage dividing device. The second sub-circuit comprises a serial connection of a second field effect transistor having a second threshold voltage, which is different from the first threshold voltage, and a second voltage dividing device. The voltage between the first field effect transistor and the first voltage dividing device is compared with the voltage between the second field effect transistor and the second voltage dividing device so that a signal may be generated at a temperature at which the ratio of a performance parameter such as on-current between the first and second field effect transistors crosses over a predefined value. The signal may be advantageously employed to actively control circuit characteristics.
摘要翻译：提供了包含第一子电路和第二子电路的并联连接的电路。第一子电路包括具有第一阈值电压的第一场效应晶体管和第一分压装置的串联连接。第二子电路包括具有与第一阈值电压不同的第二阈值电压的第二场效应晶体管的串联连接和第二分压装置。将第一场效应晶体管和第一分压装置之间的电压与第二场效应晶体管和第二分压装置之间的电压进行比较，使得可以在这样的温度下产生信号，因为第一和第二场效应晶体管之间的导通电流跨越预定值。可以有利地使用该信号来主动地控制电路特性。

14. 发明授权

US07894291B2 Circuit and method for controlling a standby voltage level of a memory 有权
标题翻译：用于控制存储器的待机电压电平的电路和方法
公开(公告)号：US07894291B2
公开(公告)日：2011-02-22
申请号：US11162847
申请日：2005-09-26
申请人： George M. Braceras , John A. Fifield , Harold Pilo
发明人： George M. Braceras , John A. Fifield , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147
摘要： A memory is provided which can be operated at an active rate of power consumption in an active operational mode and at a predetermined reduced rate of power consumption in a standby operational mode. The memory includes a current generating circuit which is operable to supply a predetermined magnitude of current to a sample power supply input terminal of a sample memory cell representative of memory cells of the memory, the predetermined magnitude of current corresponding to the predetermined reduced rate of power consumption. A voltage follower circuit is operable to output a standby voltage level equal to a voltage level at the sample power supply input terminal when the predetermined magnitude of current is supplied thereto. A memory cell array of the memory is operable to store data. In the standby operational mode, a switching circuit is operable to supply power at the standby voltage level to a power supply input terminal of the memory cell array. This permits data to remain stored in the memory during the standby mode. During an active operational mode, the switching circuit is operable to connect the power supply input terminal at the power supply to supply power at the active voltage level to the memory cell array. During the active operational mode, data can be stored into the memory cell array and retrieved from the memory cell array.
摘要翻译：提供一种存储器，其可以在主动操作模式中以在备用操作模式中以预定的降低的功率消耗速率以有效的功率消耗速率操作。存储器包括电流产生电路，其可操作以向代表存储器的存储器单元的采样存储单元的采样电源输入端提供预定大小的电流，与预定的降低的功率比相对应的预定电流值消费。电压跟随器电路可操作以当提供预定电流大小时输出等于采样电源输入端的电压电平的备用电压电平。存储器的存储单元阵列可操作以存储数据。在待机操作模式中，切换电路可操作以将备用电压电平的电力提供给存储单元阵列的电源输入端。这在待机模式期间允许数据保存在存储器中。在有效操作模式期间，开关电路可操作地连接电源处的电源输入端，以将有源电压电平的电力提供给存储单元阵列。在主动操作模式期间，可将数据存储到存储单元阵列中并从存储单元阵列检索。

15. 发明授权

US07307457B2 Apparatus for implementing dynamic data path with interlocked keeper and restore devices 有权
标题翻译：用于实现动态数据路径的装置，具有联锁保持器和恢复装置
公开(公告)号：US07307457B2
公开(公告)日：2007-12-11
申请号：US11278169
申请日：2006-03-31
申请人： George M. Braceras , John A. Fifield , Harold Pilo
发明人： George M. Braceras , John A. Fifield , Harold Pilo
IPC分类号： H03K19/096 , H03K19/094 , G11C7/00
CPC分类号： G11C7/1051 , G11C7/1057
摘要： A keeper device for dynamic logic includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during an evaluation thereof, and a second keeper path selectively coupled to the dynamic data path. The second keeper path is configured to maintain the dynamic data path at a nominal precharge level prior to an evaluation thereof, wherein the second keeper path is decoupled from the dynamic data path during the evaluation.
摘要翻译：用于动态逻辑的保持器装置包括静态耦合到动态数据路径的第一保持器路径，第一保持器路径被配置为在其评估期间防止动态数据路径的假放电，以及选择性地耦合到动态数据路径的第二保持器路径。第二保持器路径被配置为在其评估之前将动态数据路径保持在标称预充电水平，其中在评估期间第二保持器路径与动态数据路径解耦。

16. 发明申请

US20120128033A1 THERMAL SENSOR FOR SEMICONDUCTOR CIRCUITS 失效
标题翻译：用于半导体电路的热传感器
公开(公告)号：US20120128033A1
公开(公告)日：2012-05-24
申请号：US12950508
申请日：2010-11-19
申请人： Wagdi W. Abadeer , Cathryn J. Christiansen , John A. Fifield , Dimitris P. Ioannou , Tom C. Lee , Lilian Kamal
发明人： Wagdi W. Abadeer , Cathryn J. Christiansen , John A. Fifield , Dimitris P. Ioannou , Tom C. Lee , Lilian Kamal
IPC分类号： G01K7/16
CPC分类号： G01K7/16
摘要： A system and a method for measuring temperature within an operating circuit use a Wheatstone bridge within a temperature sensing circuit. One of the resistors in the Wheatstone bridge is a thermally sensitive resistive material layer within the operating circuit. The other three resistors are thermally isolated from the operating circuit. Particular configurations of NFET and PFET devices are used to provide enhanced measurement sensitivity within the temperature sensing circuit that includes the Wheatstone bridge.
摘要翻译：用于测量操作电路内的温度的系统和方法使用温度感测电路内的惠斯通电桥。惠斯通电桥中的一个电阻器是操作电路内的热敏电阻材料层。其他三个电阻器与工作电路热绝缘。 NFET和PFET器件的特殊配置用于在包括惠斯通电桥的温度检测电路中提供增强的测量灵敏度。

17. 发明授权

US07825469B2 Threshold voltage compensation for pixel design of CMOS image sensors 有权
标题翻译： CMOS图像传感器的像素设计阈值电压补偿
公开(公告)号：US07825469B2
公开(公告)日：2010-11-02
申请号：US11850488
申请日：2007-09-05
申请人： Wagdi W. Abadeer , John A. Fifield
发明人： Wagdi W. Abadeer , John A. Fifield
IPC分类号： H01L29/72
CPC分类号： H04N5/374 , H04N5/365 , H04N5/3651 , H04N5/378
摘要： The present disclosure is directed to a CMOS active pixel sensor that compensates for variations in a threshold voltage of a source follower contained therein. A structure in accordance with an embodiment includes: a replica source follower transistor; a system for creating a current in said replica source follower transistor such that a gate-source voltage of said replica source follower is substantially equal to a threshold voltage of said replica source follower; and a current mirror for biasing the isolation source follower transistor at a same current density as the replica source follower transistor.
摘要翻译：本公开涉及一种CMOS有源像素传感器，其补偿其中包含的源极跟随器的阈值电压的变化。根据实施例的结构包括：复制源极跟随器晶体管; 用于在所述复制源跟随器晶体管中产生电流的系统，使得所述复制源极跟随器的栅极 - 源极电压基本上等于所述复制源极跟随器的阈值电压; 以及电流镜，用于以与复制源极跟随器晶体管相同的电流密度偏置隔离源跟随器晶体管。

18. 发明申请

US20090243733A1 DESIGN STRUCTURE FOR TRANSFORMING AN INPUT VOLTAGE TO OBTAIN LINEARITY BETWEEN INPUT AND OUTPUT FUNCTIONS AND SYSTEM AND METHOD THEREOF 有权
标题翻译：用于变换输入电压以获得输入和输出功能与系统之间的线性的设计结构及其方法
公开(公告)号：US20090243733A1
公开(公告)日：2009-10-01
申请号：US12057686
申请日：2008-03-28
申请人： Wagdi W. Abadeer , John A. Fifield , Stephen D. Wyatt
发明人： Wagdi W. Abadeer , John A. Fifield , Stephen D. Wyatt
IPC分类号： H03L7/00
CPC分类号： H03L7/099
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a first structure for determining a non-linear characteristic of the input voltage to the output frequency response, the first design structure providing a tunneling-based current relationship with the input voltage. Also disclosed is a system and a method of implementing such structure.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括用于确定输入电压对输出频率响应的非线性特性的第一结构，第一设计结构提供与输入电压的基于隧道的电流关系。还公开了一种实现这种结构的系统和方法。

19. 发明授权

US07167053B2 Integrated circuit amplifier device and method using FET tunneling gate current 失效
标题翻译：集成电路放大器器件及使用FET隧道栅极电流的方法
公开(公告)号：US07167053B2
公开(公告)日：2007-01-23
申请号：US10904238
申请日：2004-10-29
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Kiran V. Chatty , John A. Fifield
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Kiran V. Chatty , John A. Fifield
IPC分类号： H03F3/16 , H03F3/45 , H03G3/12
CPC分类号： H03F3/16 , H03F3/45179 , H03F3/505 , H03F2203/45468
摘要： An integrated circuit amplifier includes, in an exemplary embodiment, a first field effect transistor (FET) device configured as a common source amplifier with source degeneration and a second FET device configured as a tunneling gate FET, the tunneling gate FET coupled to the source follower. The tunneling gate FET is further configured so as to set a transconductance of the amplifier and the common source amplifier with source degeneration is configured so as to set an output conductance of the amplifier.
摘要翻译：在示例性实施例中，集成电路放大器包括被配置为具有源极退化的公共源极放大器的第一场效应晶体管（FET）器件和被配置为隧道栅极FET的第二FET器件，所述隧道栅极FET耦合到源极跟随器。隧道栅极FET进一步配置为设置放大器的跨导，并且配置源极退化的公共源极放大器，以便设置放大器的输出电导。

20. 发明授权

US07061308B2 Voltage divider for integrated circuits 失效
标题翻译：用于集成电路的分压器
公开(公告)号：US07061308B2
公开(公告)日：2006-06-13
申请号：US10605466
申请日：2003-10-01
申请人： Wagdi W. Abadeer , John A. Fifield , William R. Tonti
发明人： Wagdi W. Abadeer , John A. Fifield , William R. Tonti
IPC分类号： G05F3/02
CPC分类号： G11C5/147 , H01L27/0802 , H01L27/088 , H02M3/00
摘要： A voltage divider for integrated circuits that does not include the use of resistors. In one embodiment, voltage node VDD is connected with two n-type transistors, NFET1 and NFET2, which are connected in series. NFET 1 includes a source (12), a drain (14), a gate electrode (16) having a gate area A1 (not shown), and a p-substrate (18). NFET2 includes a source (20), a drain (22), a gate electrode (24) having a gate area A2 (not shown), and a p-substrate (26). Source (12) and drain (14) of NFET1 are coupled with gate electrode (24) of NFET2. The voltage difference between NFET1 and NFET2 has a linear function with VDD. As a result, voltage VDD may be divided between NFET1 and NFET2 by properly choosing the ratio between each of the respective transistor gate electrode areas, (A1) and (A2).
摘要翻译：用于集成电路的分压器，不包括使用电阻器。在一个实施例中，电压节点VDD与串联连接的两个n型晶体管NFET 1和NFET 2连接。 NFET 1包括源极（12），漏极（14），具有栅极区域A 1（未示出）的栅电极（16）和p-衬底（18）。 NFET2包括源极（20），漏极（22），具有栅极区域A 2（未示出）的栅电极（24）和p基板（26）。 NFET 1的源极（12）和漏极（14）与NFET2的栅电极（24）耦合。 NFET 1和NFET 2之间的电压差与VDD具有线性关系。结果，通过适当地选择各个晶体管栅电极区域（A 1）和（A 2）之间的比率，可以在NFET 1和NFET 2之间划分电压VDD。

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