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11. 发明授权

US07913067B2 Method and system for overlapping execution of instructions through non-uniform execution pipelines in an in-order processor 失效
标题翻译：用于通过按顺序处理器中的非均匀执行流水线重复执行指令的方法和系统
公开(公告)号：US07913067B2
公开(公告)日：2011-03-22
申请号：US12034084
申请日：2008-02-20
申请人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung Kevin Shum
发明人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung Kevin Shum
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3857 , G06F9/3873
摘要： A system and method for overlapping execution (OE) of instructions through non-uniform execution pipelines in an in-order processor are provided. The system includes a first execution unit to perform instruction execution in a first execution pipeline. The system also includes a second execution unit to perform instruction execution in a second execution pipeline, where the second execution pipeline includes a greater number of stages than the first execution pipeline. The system further includes an instruction dispatch unit (IDU), the IDU including OE registers and logic for dispatching an OE-capable instruction to the first execution unit such that the instruction completes execution prior to completing execution of a previously dispatched instruction to the second execution unit. The system additionally includes a latch to hold a result of the execution of the OE-capable instruction until after the second execution unit completes the execution of the previously dispatched instruction.
摘要翻译：提供了一种用于通过在顺序处理器中的非均匀执行管线来重复执行（OE）指令的系统和方法。该系统包括在第一执行流水线中执行指令执行的第一执行单元。该系统还包括第二执行单元，用于在第二执行流水线中执行指令执行，其中第二执行流水线包括比第一执行流水线更多的级数。该系统还包括一个指令调度单元（IDU），该IDU包括OE寄存器和用于向第一执行单元分配一个OE能力指令的逻辑，使得指令在完成先前发送的指令执行之前完成执行单元。该系统还包括一个锁存器，用于保持执行OE能力指令的结果，直到第二执行单元完成先前发送的指令的执行。

12. 发明申请

US20090210656A1 METHOD AND SYSTEM FOR OVERLAPPING EXECUTION OF INSTRUCTIONS THROUGH NON-UNIFORM EXECUTION PIPELINES IN AN IN-ORDER PROCESSOR 失效
标题翻译：通过非订单执行管理员在订单处理程序中执行指令的方法和系统
公开(公告)号：US20090210656A1
公开(公告)日：2009-08-20
申请号：US12034084
申请日：2008-02-20
申请人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, JR. , Eric M. Schwarz , Chung-Lung Kevin Shum
发明人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, JR. , Eric M. Schwarz , Chung-Lung Kevin Shum
IPC分类号： G06F15/76 , G06F9/02 , G06F9/312
CPC分类号： G06F9/3836 , G06F9/3857 , G06F9/3873
摘要： A system and method for overlapping execution (OE) of instructions through non-uniform execution pipelines in an in-order processor are provided. The system includes a first execution unit to perform instruction execution in a first execution pipeline. The system also includes a second execution unit to perform instruction execution in a second execution pipeline, where the second execution pipeline includes a greater number of stages than the first execution pipeline. The system further includes an instruction dispatch unit (IDU), the IDU including OE registers and logic for dispatching an OE-capable instruction to the first execution unit such that the instruction completes execution prior to completing execution of a previously dispatched instruction to the second execution unit. The system additionally includes a latch to hold a result of the execution of the OE-capable instruction until after the second execution unit completes the execution of the previously dispatched instruction.
摘要翻译：提供了一种用于通过在顺序处理器中的非均匀执行管线来重复执行（OE）指令的系统和方法。该系统包括在第一执行流水线中执行指令执行的第一执行单元。该系统还包括第二执行单元，用于在第二执行流水线中执行指令执行，其中第二执行流水线包括比第一执行流水线更多的级数。该系统还包括一个指令调度单元（IDU），该IDU包括OE寄存器和用于向第一执行单元分配一个OE能力指令的逻辑，使得指令在完成先前发送的指令执行之前完成执行单元。该系统还包括一个锁存器，用于保持执行OE能力指令的结果，直到第二执行单元完成先前发送的指令的执行。

13. 发明申请

US20090210775A1 METHOD AND SYSTEM FOR INSTRUCTION ADDRESS PARITY COMPARISON 有权
标题翻译：方法和系统的指令地址的比较
公开(公告)号：US20090210775A1
公开(公告)日：2009-08-20
申请号：US12031732
申请日：2008-02-15
申请人： Fadi Y. Busaba , Brian R. Prasky , Chung-Lung Kevin Shum
发明人： Fadi Y. Busaba , Brian R. Prasky , Chung-Lung Kevin Shum
IPC分类号： G06F11/00
CPC分类号： G06F11/10
摘要： A method and system for instruction address parity comparison are provided. The method includes calculating an instruction address parity value for an instruction, and distributing the instruction address parity value to one or more functional units in processing circuitry. The method also includes receiving the distributed instruction address parity value from the one or more functional units, and calculating a completing instruction address (CIA) parity value associated with completing the instruction. The method further includes generating an error indicator in response to a mismatch between the received instruction address parity value and the CIA parity value.
摘要翻译：提供了一种用于指令地址奇偶校验比较的方法和系统。该方法包括计算指令的指令地址奇偶校验值，并将指令地址奇偶校验值分配给处理电路中的一个或多个功能单元。该方法还包括从一个或多个功能单元接收分布式指令地址奇偶校验值，以及计算与完成指令相关联的完成指令地址（CIA）奇偶校验值。该方法还包括响应于接收到的指令地址奇偶校验值和CIA奇偶校验值之间的不匹配而产生错误指示符。

14. 发明授权

US07861064B2 Method, system, and computer program product for selectively accelerating early instruction processing 失效
标题翻译：方法，系统和计算机程序产品，用于选择性加速早期指令处理
公开(公告)号：US07861064B2
公开(公告)日：2010-12-28
申请号：US12037861
申请日：2008-02-26
申请人： Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , David S. Hutton , Chung-Lung Kevin Shum
发明人： Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , David S. Hutton , Chung-Lung Kevin Shum
IPC分类号： G06F9/34 , G06F9/38
CPC分类号： G06F9/3826 , G06F9/3836
摘要： A method for selectively accelerating early instruction processing including receiving an instruction data that is normally processed in an execution stage of a processor pipeline, wherein a configuration of the instruction data allows a processing of the instruction data to be accelerated from the execution stage to an address generation stage that occurs earlier in the processor pipeline than the execution stage, determining whether the instruction data can be dispatched to the address generation stage to be processed without being delayed due to an unavailability of a processing resource needed for the processing of the instruction data in the address generation stage, dispatching the instruction data to be processed in the address generation stage if it can be dispatched without being delayed due to the unavailability of the processing resource, and dispatching the instruction data to be processed in the execution stage if it can not be dispatched without being delayed due to the unavailability of the processing resource, wherein the processing of the instruction data is selectively accelerated using an address generation interlock scheme. A corresponding system and computer program product.
摘要翻译：一种用于选择性地加速早期指令处理的方法，包括接收在处理器流水线的执行阶段中正常处理的指令数据，其中指令数据的配置允许指令数据的处理从执行阶段加速到地址在处理器流水线中比执行阶段更早发生的生成阶段，确定指令数据是否可以被分派到要处理的地址生成阶段，而不会由于处理指令数据所需的处理资源的不可用而被延迟地址生成阶段，如果能够由于处理资源的不可用而被分派而不被延迟，则在地址生成阶段调度要处理的指令数据，并且如果不能在执行阶段调度要处理的指令数据由于你而不被推迟处理资源的可用性，其中使用地址生成互锁方案选择性地加速指令数据的处理。相应的系统和计算机程序产品。

15. 发明申请

US20090217009A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING STORAGE ELEMENTS 有权
标题翻译：用于转储储存元件的系统，方法和计算机程序产品
公开(公告)号：US20090217009A1
公开(公告)日：2009-08-27
申请号：US12036520
申请日：2008-02-25
申请人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
发明人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
IPC分类号： G06F9/318
CPC分类号： G06F9/3017 , G06F9/30018 , G06F9/30101 , G06F9/355
摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.
摘要翻译：一种用于计算机系统中的翻译的系统，方法和计算机程序产品。该系统包括包含地址转换表的基地址的通用寄存器。该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

16. 发明授权

US07966474B2 System, method and computer program product for translating storage elements 有权
标题翻译：用于翻译存储元件的系统，方法和计算机程序产品
公开(公告)号：US07966474B2
公开(公告)日：2011-06-21
申请号：US12036520
申请日：2008-02-25
申请人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
发明人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
IPC分类号： G06F9/26
CPC分类号： G06F9/3017 , G06F9/30018 , G06F9/30101 , G06F9/355
摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.
摘要翻译：一种用于计算机系统中的翻译的系统，方法和计算机程序产品。该系统包括包含地址转换表的基地址的通用寄存器。该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

17. 发明授权

US08140951B2 Method and system for instruction address parity comparison 有权
标题翻译：指令地址奇偶校验比较方法和系统
公开(公告)号：US08140951B2
公开(公告)日：2012-03-20
申请号：US12031732
申请日：2008-02-15
申请人： Fadi Y. Busaba , Brian R. Prasky , Chung-Lung Kevin Shum
发明人： Fadi Y. Busaba , Brian R. Prasky , Chung-Lung Kevin Shum
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F11/10
摘要： A method and system for instruction address parity comparison are provided. The method includes calculating an instruction address parity value for an instruction, and distributing the instruction address parity value to one or more functional units in processing circuitry. The method also includes receiving the distributed instruction address parity value from the one or more functional units, and calculating a completing instruction address (CIA) parity value associated with completing the instruction. The method further includes generating an error indicator in response to a mismatch between the received instruction address parity value and the CIA parity value.
摘要翻译：提供了一种用于指令地址奇偶校验比较的方法和系统。该方法包括计算指令的指令地址奇偶校验值，并将指令地址奇偶校验值分配给处理电路中的一个或多个功能单元。该方法还包括从一个或多个功能单元接收分布式指令地址奇偶校验值，以及计算与完成指令相关联的完成指令地址（CIA）奇偶校验值。该方法还包括响应于接收到的指令地址奇偶校验值和CIA奇偶校验值之间的不匹配而产生错误指示符。

18. 发明授权

US07412476B2 Decimal multiplication for superscaler processors 失效
标题翻译：超标量处理器的十进制乘法
公开(公告)号：US07412476B2
公开(公告)日：2008-08-12
申请号：US11460296
申请日：2006-07-27
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , John G. Rell, Jr.
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , John G. Rell, Jr.
IPC分类号： G06F7/523
CPC分类号： G06F9/3001 , G06F7/496
摘要： A method for decimal multiplication in a superscaler processor comprising: obtaining a first operand and a second operand; establishing a multiplier and an effective multiplicand from the first operand and the second operand; and generating and accumulating a partial product term every two cycles. The partial product terms are created from the effective multiplicand and multiples of the multiplier, where the effective multiplicand is stored in a first register file, the multiples being ones times the effective multiplier, two times the effective multiplier, four times the effective multiplier and eight times the effective multiplier and the partial product terms are added to an accumulation of previous partial product terms shifted one digit right such that a digit shifted off is preserved as a result digit.
摘要翻译：一种用于在超标量处理器中进行十进制相乘的方法，包括：获得第一操作数和第二操作数; 从第一个操作数和第二个操作数建立乘数和有效的被乘数; 并且每两个周期产生和累积部分乘积项。部分乘积项是从乘法器的有效乘数和乘数创建的，其中有效被乘数存储在第一个寄存器文件中，倍数是有效乘数的倍数，有效乘数的两倍，有效乘数的四倍和八倍乘以有效乘数和部分乘积项添加到前一个部分乘积项的累积中，该乘积项被移位一位数字，使得数字移位被保留为结果位。

19. 发明授权

US07490121B2 Modular binary multiplier for signed and unsigned operands of variable widths 有权
标题翻译：具有可变宽度的有符号和无符号操作数的模块二进制乘法器
公开(公告)号：US07490121B2
公开(公告)日：2009-02-10
申请号：US11749239
申请日：2007-05-16
申请人： Fadi Y. Busaba , Steven R. Carlough , David S. Hutton , Christopher A. Krygowski , John G. Rell, Jr. , Sheryll H. Veneracion
发明人： Fadi Y. Busaba , Steven R. Carlough , David S. Hutton , Christopher A. Krygowski , John G. Rell, Jr. , Sheryll H. Veneracion
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F7/5332 , G06F9/30014 , G06F2207/3816
摘要： A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgroups; in the event the multiplicand is larger than a selected length, partitioning the multiplicand into a plurality of multiplicand subgroups and at least one of zeroing out of unused bits of the multiplicand subgroup and sign-extending a smaller portion of the multiplicand subgroup; establishing a plurality of multiplicand multiples based on at least one of a selected multiplicand subgroup of the plurality of multiplicand subgroups and the multiplicand; selecting one or more of the multiplicand multiples of the plurality of multiplicand multiples based on the each multiplier subgroup of the plurality of multiplier subgroups; and generating a first modular product based on the selected multiplicand multiples.
摘要翻译：在处理设备中实现二进制乘法的方法包括从存储设备获取乘法器和乘法器; 在乘数大于选定长度的情况下，将乘法器分成多个乘法器子组; 在所述被乘数大于所选择的长度的情况下，将所述被乘数划分为多个被乘数的子组和被乘数子组的未使用的比特中的至少一个，并对被乘数子组的较小部分进行符号扩展; 基于所述多个被乘数子组和被乘数中的所选择的被乘数子群中的至少一个，建立多个被乘数; 基于所述多个乘法器子组中的每个乘法器子组来选择所述多个被乘数中的一个或多个被乘数; 以及基于所选择的被乘数生成第一模块化产品。

20. 发明授权

US08201067B2 Processor error checking for instruction data 有权
标题翻译：处理器错误检查指令数据
公开(公告)号：US08201067B2
公开(公告)日：2012-06-12
申请号：US12037038
申请日：2008-02-25
申请人： Fadi Y. Busaba , Khary J. Alexander , Michael Billeci , Bruce C. Giamei , Vimal M. Kapadia
发明人： Fadi Y. Busaba , Khary J. Alexander , Michael Billeci , Bruce C. Giamei , Vimal M. Kapadia
IPC分类号： G06F11/00 , G08C25/00 , H03M13/00 , H04L1/00
CPC分类号： G06F11/10
摘要： A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.
摘要翻译：一种用于处理器错误检查的方法，包括接收指令数据，基于指令数据产生预处理奇偶校验数据，维持预处理奇偶校验数据，处理指令数据，基于处理指令产生后处理奇偶校验数据数据，通过将后处理奇偶校验数据与预处理奇偶校验数据进行比较来检查与处理指令数据相关的错误，以及如果后处理奇偶校验数据发送指示与处理指令数据相关的错误的错误信号数据与预处理奇偶校验数据不匹配，其中在不使用重复处理电路的情况下执行检查与处理指令数据有关的错误。

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