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11. 发明授权

US4550031A Control of Si doping in GaAs, (Al,Ga)As and other compound semiconductors during MBE growth 失效
标题翻译：在MBE生长期间控制GaAs，（Al，Ga）As和其他化合物半导体中的Si掺杂
公开(公告)号：US4550031A
公开(公告)日：1985-10-29
申请号：US674794
申请日：1984-11-26
申请人： Jonathan K. Abrokwah
发明人： Jonathan K. Abrokwah
IPC分类号： C30B23/02 , C30B23/08 , B05D3/06
CPC分类号： C30B29/40 , C30B23/002 , C30B23/08
摘要： A method of modulation doping GaAs, (Al,Ga)As and related compounds with silicon ions during molecular beam epitaxy (MBE) growth.
摘要翻译：在分子束外延（MBE）生长期间调制掺杂GaAs，（Al，Ga）As和与硅离子的相关化合物的方法。

12. 发明授权

US08847280B2 Insulated gate field effect transistors 有权
标题翻译：绝缘栅场效应晶体管
公开(公告)号：US08847280B2
公开(公告)日：2014-09-30
申请号：US13293910
申请日：2011-11-10
申请人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
发明人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
IPC分类号： H01L29/78 , H01L23/31 , H01L29/778 , H01L29/51 , H01L29/207
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译：通过提供期望地包括III-V半导体的衬底来获得改进的绝缘栅场效应器件，所述衬底在衬底上具有另外的半导体层，其适于在形成在半导体层上的间隔开的源 - 漏电极之间容纳器件的沟道。在半导体层上形成介电层。在电介质层上形成密封层并暴露于氧等离子体。在源 - 漏电极之间的电介质层上形成栅电极。电介质层优选包含氧化镓和/或钆 - 镓氧化物，氧等离子体优选为电感耦合等离子体。希望在密封层的上方设置另外的例如氮化硅的密封层。否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。

13. 发明授权

US08105925B2 Method for forming an insulated gate field effect device 有权
标题翻译：一种形成绝缘栅场效应器件的方法
公开(公告)号：US08105925B2
公开(公告)日：2012-01-31
申请号：US12182349
申请日：2008-07-30
申请人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
发明人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
IPC分类号： H01L21/26
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28). Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译：通过提供期望地包括III-V半导体的衬底（20）来获得改进的绝缘栅场效应器件（60），所述衬底（20）在所述衬底（20）上具有另外的半导体层（22），所述半导体层适于容纳所述沟道（230）所述器件（60）形成在所述半导体层（22）上形成的间隔开的源 - 漏电极（421,422）之间。在半导体层（22）上形成介电层（24）。密封层（28）形成在电介质层（24）上并暴露于氧等离子体（36）。在源漏电极（421,422）之间的电介质层（24）上形成栅电极（482）。电介质层（24）优选包含氧化镓（25）和/或氧化钆 - 氧化镓（26,27），氧等离子体（36）优选为电感耦合等离子体。期望地在密封层（28）的上方设置例如氮化硅的另外的密封层（44）。否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。

14. 发明授权

US07842587B2 III-V MOSFET fabrication and device 有权
标题翻译： III-V MOSFET制造和器件
公开(公告)号：US07842587B2
公开(公告)日：2010-11-30
申请号：US12022942
申请日：2008-01-30
申请人： Matthias Passlack , Jonathan K. Abrokwah , Karthik Rajagopalan , Haiping Zhou , Richard J. Hill , Xu Li , David A. Moran , Iain G. Thayne , Peter Zurcher
发明人： Matthias Passlack , Jonathan K. Abrokwah , Karthik Rajagopalan , Haiping Zhou , Richard J. Hill , Xu Li , David A. Moran , Iain G. Thayne , Peter Zurcher
IPC分类号： H01L21/20
CPC分类号： H01L29/78 , H01L29/20 , H01L29/66462 , H01L29/7785
摘要： A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45° to 90°. A metal contact structure (130) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap (133) between the two. The wafer (100) is heat treated, which causes migration of at least one of the metal elements to form an alloy region (137) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer (140,150) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.
摘要翻译：半导体制造工艺包括形成覆盖在包括III-V半导体化合物的衬底（101）上的栅极电介质层（120）。栅极介电层被图案化以产生具有基本上垂直的侧壁（127）的栅极电介质结构（121），例如大约45°至90°的斜率。金属接触结构（130）形成在晶片衬底上。接触结构被充分地从栅极电介质结构侧向移位以限定两者之间的间隙（133）。对晶片（100）进行热处理，这导致至少一种金属元素迁移，从而在下面的晶片衬底中形成合金区域（137）。合金区域位于接触结构的下面，并且延伸穿过位于间隙下方的晶片衬底的全部或一部分。然后形成绝缘或介电覆盖层（140,150），覆盖晶片并覆盖由间隙暴露的衬底的部分。

15. 发明授权

US07683733B2 Balun transformer with improved harmonic suppression 有权
标题翻译：平衡变压器具有改进的谐波抑制
公开(公告)号：US07683733B2
公开(公告)日：2010-03-23
申请号：US12025315
申请日：2008-02-04
申请人： Qiang Li , Jonathan K. Abrokwah , Olin L. Hartin , Lianjun Liu
发明人： Qiang Li , Jonathan K. Abrokwah , Olin L. Hartin , Lianjun Liu
IPC分类号： H03H7/42 , H01P5/00
CPC分类号： H01F19/04 , H03H7/1775 , H03H7/42 , H03H2001/0064 , Y10T29/4902
摘要： An electronic assembly includes a substrate (66), a balun transformer (42) formed on the substrate (66) and including a first winding (50) and a second winding (52), each having respective first and second ends, and a reaction circuit component (48) formed on the substrate (66) and electrically coupled to the second winding (52) between the first and second ends thereof. The balun transformer (42) and the reaction circuit component (48) jointly form a harmonically suppressed balun transformer having a fundamental frequency, and the reaction circuit component (48) is tuned such that the harmonically suppressed balun transformer resonates at a selected harmonic of the fundamental frequency.
摘要翻译：电子组件包括衬底（66），形成在衬底（66）上并包括第一绕组（50）和第二绕组（52）的平衡不平衡变压器（42），每个具有相应的第一和第二端，以及反应电路部件（48），形成在所述基板（66）上并且在所述第一和第二端之间电连接到所述第二绕组（52）。平衡 - 不平衡变压器（42）和反应电路部件（48）共同形成具有基频的谐波抑制平衡不平衡变压器，并且调谐反应电路部件（48），使得谐波抑制的平衡不平衡变压器以所选择的谐波谐振基频

16. 发明授权

US06022410A Alkaline-earth metal silicides on silicon 失效
标题翻译：硅上的碱土金属硅化物
公开(公告)号：US06022410A
公开(公告)日：2000-02-08
申请号：US144921
申请日：1998-09-01
申请人： Zhiyi Yu , Jun Wang , Ravindranath Droopad , Daniel S. Marshall , Jerald A. Hallmark , Jonathan K. Abrokwah
发明人： Zhiyi Yu , Jun Wang , Ravindranath Droopad , Daniel S. Marshall , Jerald A. Hallmark , Jonathan K. Abrokwah
IPC分类号： H01L21/203 , C30B23/02 , C30B29/10 , C30B23/00
CPC分类号： C30B23/02 , C30B29/10
摘要： A method of forming a thin silicide layer on a silicon substrate 12 including heating the surface of the substrate to a temperature of approximately 500.degree. C. to 750.degree. C. and directing an atomic beam of silicon 18 and an atomic beam of an alkaline-earth metal 20 at the heated surface of the substrate in a molecular beam epitaxy chamber at a pressure in a range below 10.sup.-9 Torr. The silicon to alkaline-earth metal flux ratio is kept constant (e.g. Si/Ba flux ratio is kept at approximately 2:1) so as to form a thin alkaline-earth metal silicide layer (e.g. BaSi.sub.2) on the surface of the substrate. The thickness is determined by monitoring in situ the surface of the single crystal silicide layer with RHEED and terminating the atomic beam when the silicide layer is a selected submonolayer to one monolayer thick.
摘要翻译：一种在硅衬底12上形成薄硅化物层的方法，包括将衬底的表面加热至约500℃至750℃的温度，并引导硅18的原子束和碱性电子束的原子束，在分子束外延室中的衬底的加热表面处的压力在10-9乇以下的地球金属20。将硅与碱土金属的通量比保持恒定（例如，Si / Ba通量比保持在约2:1），以在衬底的表面上形成薄的碱土金属硅化物层（例如BaSi 2）。通过用RHEED原位监测单晶硅化物层的表面并且当硅化物层是选择的亚单层至一个单层厚度时终止原子束来确定厚度。

17. 发明授权

US5693544A N-type higfet and method 失效
标题翻译： N型高度和方法
公开(公告)号：US5693544A
公开(公告)日：1997-12-02
申请号：US616293
申请日：1996-03-15
申请人： Jonathan K. Abrokwah , Rodolfo Lucero , Jeffrey A. Rollman
发明人： Jonathan K. Abrokwah , Rodolfo Lucero , Jeffrey A. Rollman
IPC分类号： H01L29/812 , H01L21/285 , H01L21/335 , H01L21/338 , H01L29/778 , H01L29/80 , H01L21/265 , H01L21/00 , H01L21/20 , H01L21/30
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/802
摘要： An N-type HIGFET (10) utilizes two etch layers (17,18) to form a gate insulator (16) to be shorter that the gate electrode (21). This T-shaped gate structure facilitates forming source (23) and drain (24) regions that are separated from the gate insulator (16) by a distance (22) in order to reduce leakage current and increase the breakdown voltage.
摘要翻译： N型HIGFET（10）利用两个蚀刻层（17,18）形成栅极电极（21）的栅极绝缘体（16）更短。这种T形栅极结构有助于形成与栅极绝缘体（16）分离距离（22）的源极（23）和漏极（24）区域，以便减少漏电流并增加击穿电压。

18. 发明授权

US5614739A HIGFET and method 失效
标题翻译： HIGFET和方法
公开(公告)号：US5614739A
公开(公告)日：1997-03-25
申请号：US459854
申请日：1995-06-02
申请人： Jonathan K. Abrokwah , Rodolfo Lucero , Jeffrey A. Rollman
发明人： Jonathan K. Abrokwah , Rodolfo Lucero , Jeffrey A. Rollman
IPC分类号： H01L29/812 , H01L21/033 , H01L21/311 , H01L21/335 , H01L21/338 , H01L29/778 , H01L29/80 , H01L31/0328 , H01L29/76 , H01L31/0336
CPC分类号： H01L29/66462 , H01L21/0338 , H01L21/31144 , H01L29/802
摘要： A HIGFET (10) utilizes an etch stop layer (17) to form a gate insulator (16) to be narrower than the gate electrode (21). This T-shaped gate structure facilitates forming source (23) and drain (24) regions that are separated from the gate insulator (16) by a distance (22) in order to reduce leakage current and increase the breakdown voltage.
摘要翻译： HIGFET（10）利用蚀刻停止层（17）形成窄于栅电极（21）的栅极绝缘体（16）。这种T形栅极结构有助于形成与栅极绝缘体（16）分离距离（22）的源极（23）和漏极（24）区域，以便减少漏电流并增加击穿电压。

19. 发明申请

US20120056246A1 INSULATED GATE FIELD EFFECT TRANSISTORS 有权
标题翻译：绝缘栅场效应晶体管
公开(公告)号：US20120056246A1
公开(公告)日：2012-03-08
申请号：US13293910
申请日：2011-11-10
申请人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
发明人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
IPC分类号： H01L29/78
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译：通过提供期望地包括III-V半导体的衬底来获得改进的绝缘栅场效应器件，所述衬底在衬底上具有另外的半导体层，其适于在形成在半导体层上的间隔开的源 - 漏电极之间容纳器件的沟道。在半导体层上形成介电层。在电介质层上形成密封层并暴露于氧等离子体。在源 - 漏电极之间的电介质层上形成栅电极。电介质层优选包含氧化镓和/或钆 - 镓氧化物，氧等离子体优选为电感耦合等离子体。希望在密封层的上方设置另外的例如氮化硅的密封层。否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。

20. 发明申请

US20090189252A1 III-V MOSFET Fabrication and Device 有权
标题翻译： III-V MOSFET制造和器件
公开(公告)号：US20090189252A1
公开(公告)日：2009-07-30
申请号：US12022942
申请日：2008-01-30
申请人： Matthias Passlack , Jonathan K. Abrokwah , Karthik Rajagopalan , Haiping Zhou , Richard J. Hill , Xu Li , David A. Moran , Iain G. Thayne , Peter Zurcher
发明人： Matthias Passlack , Jonathan K. Abrokwah , Karthik Rajagopalan , Haiping Zhou , Richard J. Hill , Xu Li , David A. Moran , Iain G. Thayne , Peter Zurcher
IPC分类号： H01L21/334 , H01L29/20
CPC分类号： H01L29/78 , H01L29/20 , H01L29/66462 , H01L29/7785
摘要： A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45° to 90°. A metal contact structure (130) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap (133) between the two. The wafer (100) is heat treated, which causes migration of at least one of the metal elements to form an alloy region (137) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer (140,150) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.
摘要翻译：半导体制造工艺包括形成覆盖在包括III-V半导体化合物的衬底（101）上的栅极电介质层（120）。栅极介电层被图案化以产生具有基本上垂直的侧壁（127）的栅极电介质结构（121），例如大约45°至90°的斜率。金属接触结构（130）形成在晶片衬底上。接触结构被充分地从栅极电介质结构侧向移位以限定两者之间的间隙（133）。对晶片（100）进行热处理，这导致至少一种金属元素迁移，从而在下面的晶片衬底中形成合金区域（137）。合金区域位于接触结构的下面，并且延伸穿过位于间隙下方的晶片衬底的全部或一部分。然后形成绝缘或介电覆盖层（140,150），覆盖晶片并覆盖由间隙暴露的衬底的部分。

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