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11. 发明申请

US20120305940A1 Defect Free Si:C Epitaxial Growth 审中-公开
标题翻译：缺陷Si：C外延生长
公开(公告)号：US20120305940A1
公开(公告)日：2012-12-06
申请号：US13151238
申请日：2011-06-01
申请人： Thomas N. Adam , Stephen W. Bedell , Bruce B. Doris , Lisa F. Edge , Keith E. Fogel , Johnathan E. Faltermeier , Jinghong Li , Alexander Reznicek , Devendra K. Sadana , Bin Yang
发明人： Thomas N. Adam , Stephen W. Bedell , Bruce B. Doris , Lisa F. Edge , Keith E. Fogel , Johnathan E. Faltermeier , Jinghong Li , Alexander Reznicek , Devendra K. Sadana , Bin Yang
IPC分类号： H01L29/24 , H01L21/20
CPC分类号： H01L21/02529 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L29/045 , H01L29/66636 , H01L29/7848 , H01L29/78654
摘要： A method and structure are disclosed for a defect free Si:C source/drain in an NFET device. A wafer is accepted with a primary surface of {100} crystallographic orientation. A recess is formed in the wafer in such manner that the bottom surface and the four sidewall surfaces of the recess are all having {100} crystallographic orientations. A Si:C material is eptaxially grown in the recess, and due to the crystallographic orientations the defect density next to each of the four sidewall surfaces is essentially the same as next to the bottom surface. The epitaxially filled recess is used in the source/drain fabrication of an NFET device. The NFET device is oriented along the crystallographic direction, and has the device channel under a tensile strain due to the defect free Si:C in the source/drain.
摘要翻译：公开了在NFET器件中的无缺陷Si：C源极/漏极的方法和结构。接受具有{100}晶体取向的主表面的晶片。以这样的方式在晶片中形成凹部，使得凹部的底表面和四个侧壁表面都具有{100}晶体取向。 Si：C材料在凹槽中被轴向生长，并且由于晶体取向，邻近四个侧壁表面的缺陷密度基本上与下表面相同。外延填充的凹槽用于NFET器件的源极/漏极制造。 NFET器件沿着<100>结晶方向取向，由于源极/漏极中的缺陷Si：C，器件沟道处于拉伸应变状态。

12. 发明授权

US08933515B2 Device structure, layout and fabrication method for uniaxially strained transistors 有权
标题翻译：单轴应变晶体管的器件结构，布局和制造方法
公开(公告)号：US08933515B2
公开(公告)日：2015-01-13
申请号：US13531175
申请日：2012-06-22
申请人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
发明人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
IPC分类号： H01L27/088 , H01L21/8238 , H01L27/02 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/6656 , H01L29/66628 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.
摘要翻译：一种用于制造半导体器件的半导体器件和方法包括提供具有第一应变轴的应变半导体层，在应变半导体层的表面内形成有源区，其中有源区具有沿应变轴的纵向轴线并形成栅极结构在活跃地区。在应变半导体层的表面上方和与栅极结构相邻的有源区上形成升高的源/漏区，以形成晶体管器件。

13. 发明申请

US20110254015A1 METHOD FOR IMPROVING DEVICE PERFORMANCE USING EPITAXIALLY GROWN SILICON CARBON (SiC) OR SILICON-GERMANIUM (SiGe) 有权
标题翻译：使用外延硅碳化硅（SiC）或硅锗（SiGe）改善器件性能的方法
公开(公告)号：US20110254015A1
公开(公告)日：2011-10-20
申请号：US12760688
申请日：2010-04-15
申请人： Bruce B. Doris , Johnathan E. Faltermeier , Lahir M. Shaik Adam , Balasubramanian S. Pranatharthi Haran
发明人： Bruce B. Doris , Johnathan E. Faltermeier , Lahir M. Shaik Adam , Balasubramanian S. Pranatharthi Haran
IPC分类号： H01L29/78 , H01L21/336 , H01L29/24
CPC分类号： H01L29/66636 , H01L21/02576 , H01L21/02579 , H01L21/223 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/2807 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/6659 , H01L29/7848
摘要： A semiconductor substrate including a field effect transistor (FET) and a method of producing the same wherein a stressor is provided in a recess before the source/drain region is formed. The device has an increased carrier mobility in the channel region adjacent to the gate electrode.
摘要翻译：包括场效应晶体管（FET）的半导体衬底及其制造方法，其中在形成源极/漏极区域之前的凹部中设置应力器。器件在与栅电极相邻的沟道区域中具有增加的载流子迁移率。

14. 发明申请

US20100048027A1 Smooth and vertical semiconductor fin structure 有权
标题翻译：平滑和垂直的半导体鳍结构
公开(公告)号：US20100048027A1
公开(公告)日：2010-02-25
申请号：US12195691
申请日：2008-08-21
申请人： Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ying Zhang
IPC分类号： H01L21/302
CPC分类号： H01L21/30608 , H01L29/045 , H01L29/66795
摘要： A method for processing a semiconductor fin structure is disclosed. The method includes thermal annealing a fin structure in an ambient containing an isotope of hydrogen. Following the thermal annealing step, the fin structure is etched in a crystal-orientation dependent, self-limiting, manner. The crystal-orientation dependent etch may be selected to be an aqueous solution containing ammonium hydroxide (NH4OH). The completed fin structure has smooth sidewalls and a uniform thickness profile. The fin structure sidewalls are {110} planes.
摘要翻译：公开了一种半导体鳍片结构的处理方法。该方法包括在含有氢同位素的环境中对翅片结构进行热退火。在热退火步骤之后，鳍结构被蚀刻成晶体取向的自限制的方式。取决于晶体取向的蚀刻可以选择为含有氢氧化铵（NH 4 OH）的水溶液。完成的翅片结构具有平滑的侧壁和均匀的厚度轮廓。翅片结构侧壁是{110}平面。

15. 发明授权

US09331174B2 Method for improving device performance using epitaxially grown silicon carbon (SiC) or silicon-germanium (SiGe) 有权
标题翻译：使用外延生长硅（SiC）或硅 - 锗（SiGe）改善器件性能的方法
公开(公告)号：US09331174B2
公开(公告)日：2016-05-03
申请号：US12760688
申请日：2010-04-15
申请人： Bruce B. Doris , Johnathan E. Faltermeier , Lahir M. Shaik Adam , Balasubramanian S. Pranatharthi Haran
发明人： Bruce B. Doris , Johnathan E. Faltermeier , Lahir M. Shaik Adam , Balasubramanian S. Pranatharthi Haran
IPC分类号： H01L29/66 , H01L29/78 , H01L21/02 , H01L21/223 , H01L21/265 , H01L21/28 , H01L29/165 , H01L29/49 , H01L29/51
CPC分类号： H01L29/66636 , H01L21/02576 , H01L21/02579 , H01L21/223 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/2807 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/6659 , H01L29/7848
摘要： A semiconductor substrate including a field effect transistor (FET) and a method of producing the same wherein a stressor is provided in a recess before the source/drain region is formed. The device has an increased carrier mobility in the channel region adjacent to the gate electrode.
摘要翻译：包括场效应晶体管（FET）的半导体衬底及其制造方法，其中在形成源极/漏极区域之前的凹部中设置应力器。器件在与栅电极相邻的沟道区域中具有增加的载流子迁移率。

16. 发明授权

US08288218B2 Device structure, layout and fabrication method for uniaxially strained transistors 有权
标题翻译：单轴应变晶体管的器件结构，布局和制造方法
公开(公告)号：US08288218B2
公开(公告)日：2012-10-16
申请号：US12689346
申请日：2010-01-19
申请人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
发明人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/6656 , H01L29/66628 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.
摘要翻译：一种用于制造半导体器件的半导体器件和方法包括提供具有第一应变轴的应变半导体层，在应变半导体层的表面内形成有源区，其中有源区具有沿应变轴的纵向轴线并形成栅极结构在活跃地区。在应变半导体层的表面上方和与栅极结构相邻的有源区上形成升高的源/漏区，以形成晶体管器件。

17. 发明申请

US20110031503A1 DEVICE WITH STRESSED CHANNEL 审中-公开
标题翻译：具有应力通道的设备
公开(公告)号：US20110031503A1
公开(公告)日：2011-02-10
申请号：US12538627
申请日：2009-08-10
申请人： Bruce B. Doris , Johnathan E. Faltermeier , Lahir S. Adam , Balasubramanian S. Haran
发明人： Bruce B. Doris , Johnathan E. Faltermeier , Lahir S. Adam , Balasubramanian S. Haran
IPC分类号： H01L29/161 , H01L27/092 , H01L21/04 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An FET device is disclosed which contains a source and a drain that are each provided with an extension. The source and the drain, and their extensions, are composed of epitaxial materials containing Ge or C. The epitaxial materials and the Si substrate have differing lattice constants, consequently the source and the drain and their extensions are imparting a state of stress onto the channel. For a PFET device the epitaxial material may be SiGe, or Ge, and the channel may be in a compressive state of stress. For an NFET device the epitaxial material may be SiC and the channel may be in a tensile state of stress. A method for fabricating an FET device is also disclosed. One may form a first recession in the Si substrate to a first depth on opposing sides of the gate. The first recession is filled epitaxially with a first epitaxial material. Then, a second recession may be formed in the Si substrate to a second depth, which is greater than the first depth. Next, one may fill the second recession with a second epitaxial material, which is the same kind of material as the first epitaxial material. The epitaxial materials are selected to have a different lattice constant than the Si substrate, and consequently a state of stress is being imparted onto the channel.
摘要翻译：公开了一种FET器件，其包含各自具有延伸部的源极和漏极。源极和漏极及其延伸部分由包含Ge或C的外延材料组成。外延材料和Si衬底具有不同的晶格常数，因此源极和漏极及其延伸部分在沟道上赋予应力状态。对于PFET器件，外延材料可以是SiGe或Ge，并且沟道可以处于压应力的压缩状态。对于NFET器件，外延材料可以是SiC，并且沟道可以处于应力的拉伸状态。还公开了一种用于制造FET器件的方法。可以在Si衬底中形成第一凹陷到栅极的相对侧上的第一深度。用第一外延材料外延地填充第一次衰退。然后，可以在Si衬底中形成比第一深度更大的第二深度的第二凹陷。接下来，可以用与第一外延材料相同的材料的第二外延材料填充第二凹陷。选择外延材料具有与Si衬底不同的晶格常数，并且因此在沟道上施加应力状态。

18. 发明申请

US20110175164A1 DEVICE STRUCTURE, LAYOUT AND FABRICATION METHOD FOR UNIAXIALLY STRAINED TRANSISTORS 有权
标题翻译：非均匀应变晶体管的器件结构，布局和制造方法
公开(公告)号：US20110175164A1
公开(公告)日：2011-07-21
申请号：US12689346
申请日：2010-01-19
申请人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-chen Yeh
发明人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-chen Yeh
IPC分类号： H01L27/12 , H01L21/86
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/6656 , H01L29/66628 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.
摘要翻译：一种用于制造半导体器件的半导体器件和方法包括提供具有第一应变轴的应变半导体层，在应变半导体层的表面内形成有源区，其中有源区具有沿应变轴的纵向轴线并形成栅极结构在活跃地区。在应变半导体层的表面上方和与栅极结构相邻的有源区上形成升高的源/漏区，以形成晶体管器件。

19. 发明授权

US08268729B2 Smooth and vertical semiconductor fin structure 有权
标题翻译：平滑和垂直的半导体鳍结构
公开(公告)号：US08268729B2
公开(公告)日：2012-09-18
申请号：US12195691
申请日：2008-08-21
申请人： Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ying Zhang
IPC分类号： H01L21/302 , H01L21/324
CPC分类号： H01L21/30608 , H01L29/045 , H01L29/66795
摘要： A method for processing a semiconductor fin structure is disclosed. The method includes thermal annealing a fin structure in an ambient containing an isotope of hydrogen. Following the thermal annealing step, the fin structure is etched in a crystal-orientation dependent, self-limiting, manner. The crystal-orientation dependent etch may be selected to be an aqueous solution containing ammonium hydroxide (NH4OH). The completed fin structure has smooth sidewalls and a uniform thickness profile. The fin structure sidewalls are {110} planes.
摘要翻译：公开了一种半导体鳍片结构的处理方法。该方法包括在含有氢同位素的环境中对翅片结构进行热退火。在热退火步骤之后，鳍结构被蚀刻成晶体取向的自限制的方式。取决于晶体取向的蚀刻可以选择为含有氢氧化铵（NH 4 OH）的水溶液。完成的翅片结构具有平滑的侧壁和均匀的厚度轮廓。翅片结构侧壁是{110}平面。

20. 发明授权

US09041116B2 Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs) 有权
公开(公告)号：US09041116B2
公开(公告)日：2015-05-26
申请号：US13478154
申请日：2012-05-23
申请人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
发明人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
IPC分类号： H01L27/092 , H01L27/12 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

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