专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08507317B2 Solder bump structure for flip chip semiconductor devices and method of manufacturing therefore 有权
标题翻译：因此，倒装芯片半导体器件的焊接凸块结构及其制造方法
公开(公告)号：US08507317B2
公开(公告)日：2013-08-13
申请号：US13093032
申请日：2011-04-25
申请人： Mark A. Bachman , Donald S. Bitting , Sailesh Chittipeddi , Seung H. Kang , Sailesh M. Merchant
发明人： Mark A. Bachman , Donald S. Bitting , Sailesh Chittipeddi , Seung H. Kang , Sailesh M. Merchant
IPC分类号： H01L21/60
CPC分类号： H01L24/14 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02125 , H01L2224/0401 , H01L2224/05006 , H01L2224/05022 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05568 , H01L2224/13007 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/00012 , H01L2224/05552
摘要： The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening.
摘要翻译：本发明在一个方面提供一种半导体器件，其包括位于半导体衬底之上的互连层。钝化层位于互连层上并且具有形成在其中的焊料凸块支撑开口。包括导电材料的支撑柱位于焊料凸块支撑开口内。

12. 发明授权

US07804291B2 Semiconductor test device with heating circuit 有权
标题翻译：带加热电路的半导体测试装置
公开(公告)号：US07804291B2
公开(公告)日：2010-09-28
申请号：US11673714
申请日：2007-02-12
申请人： Seung H. Kang , Lisa E. Mullin , Subramanian Karthikeyan , Sailesh M. Merchant
发明人： Seung H. Kang , Lisa E. Mullin , Subramanian Karthikeyan , Sailesh M. Merchant
IPC分类号： G01R31/00 , G01R31/319 , G01R31/28
CPC分类号： G01R31/2877 , G01R31/2856
摘要： A semiconductor test device includes a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit. The semiconductor test device also includes an integrally formed heating circuit comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.
摘要翻译：半导体测试装置包括具有用于施加电信号和测量测试电路的电参数的触点的测试电路。半导体测试装置还包括整体形成的加热电路，其包括邻近测试电路定位的至少一个电路弯道，用于升高测试电路的一部分内的温度。

13. 发明授权

US07388395B2 Test semiconductor device and method for determining Joule heating effects in such a device 有权
标题翻译：测试这种器件中的焦耳加热效应的半导体器件和方法
公开(公告)号：US07388395B2
公开(公告)日：2008-06-17
申请号：US11403750
申请日：2006-04-13
申请人： Seung H. Kang , Subramanian Karthikeyan , Sailesh M. Merchant
发明人： Seung H. Kang , Subramanian Karthikeyan , Sailesh M. Merchant
IPC分类号： G01R31/26
CPC分类号： G01R31/2877 , G01R31/2853 , G01R31/2856 , H01L22/32
摘要： Method and test structures for determining heating effects in a test semiconductor device (10) are provided. The test device may include a first conductive metal structure (151-156) for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate (121-126) the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.
摘要翻译：提供了用于确定测试半导体器件（10）中的加热效应的方法和测试结构。测试装置可以包括用于接受引起加热效应的电流的第一导电金属结构（15 SUB-15 6）。测试装置还可以包括靠近第一导电结构的第二导电金属结构，用于响应于加热效应而获得电阻率变化。电阻率变化表示由于加热效应引起的温度变化。

14. 发明授权

US07952206B2 Solder bump structure for flip chip semiconductor devices and method of manufacture therefore 有权
标题翻译：因此，用于倒装芯片半导体器件的焊接凸块结构及其制造方法
公开(公告)号：US07952206B2
公开(公告)日：2011-05-31
申请号：US11459249
申请日：2006-07-21
申请人： Mark A. Bachman , Donald S. Bitting , Sailesh Chittipeddi , Seung H. Kang , Sailesh M. Merchant
发明人： Mark A. Bachman , Donald S. Bitting , Sailesh Chittipeddi , Seung H. Kang , Sailesh M. Merchant
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/14 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02125 , H01L2224/0401 , H01L2224/05006 , H01L2224/05022 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05568 , H01L2224/13007 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/00012 , H01L2224/05552
摘要： The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening.
摘要翻译：本发明在一个方面提供一种半导体器件，其包括位于半导体衬底之上的互连层。钝化层位于互连层上并且具有形成在其中的焊料凸块支撑开口。包括导电材料的支撑柱位于焊料凸块支撑开口内。

15. 发明授权

US07061264B2 Test semiconductor device and method for determining Joule heating effects in such a device 有权
标题翻译：测试这种器件中的焦耳加热效应的半导体器件和方法
公开(公告)号：US07061264B2
公开(公告)日：2006-06-13
申请号：US10953292
申请日：2004-09-29
申请人： Seung H. Kang , Subramanian Karthikeyan , Sailesh M. Merchant
发明人： Seung H. Kang , Subramanian Karthikeyan , Sailesh M. Merchant
IPC分类号： G01R31/26
CPC分类号： G01R31/2877 , G01R31/2853 , G01R31/2856 , H01L22/32
摘要： Method and test structures for determining heating effects in a test semiconductor device (10) are provided. The test device may include a first conductive metal structure (151–156) for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate (121–126) the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.
摘要翻译：提供了用于确定测试半导体器件（10）中的加热效应的方法和测试结构。测试装置可以包括用于接受引起加热效应的电流的第一导电金属结构（15 SUB-15,6）。测试装置还可以包括靠近第一导电结构的第二导电金属结构，用于响应于加热效应而获得电阻率变化。电阻率变化表示由于加热效应引起的温度变化。

16. 发明授权

US08987137B2 Method of fabrication of through-substrate vias 有权
标题翻译：贯穿基板通孔的制造方法
公开(公告)号：US08987137B2
公开(公告)日：2015-03-24
申请号：US12969836
申请日：2010-12-16
申请人： Mark A. Bachman , Sailesh M. Merchant , John Osenbach
发明人： Mark A. Bachman , Sailesh M. Merchant , John Osenbach
IPC分类号： H01L21/44 , H01L21/768 , H01L25/065
CPC分类号： H01L21/76898 , H01L25/0657 , H01L2224/08145 , H01L2224/80894 , H01L2224/80895 , H01L2224/80896 , H01L2225/06513 , H01L2225/06541
摘要： A method of manufacturing a through-substrate-via structure. The method comprises providing a substrate having a front-side and an opposite back-side. A through-substrate via opening is formed in the front-side of the substrate. The through-substrate-via opening does not penetrate an outer surface of the back-side of the substrate. The through-substrate-via opening is filled with a solid fill material. Portions of the substrate from the outer surface of the back-side of the substrate are removed to thereby expose the fill material. At least portions of the exposed fill material are removed to form a back-side through-substrate via opening that traverses an entire thickness of the substrate. The back-side through-substrate via opening is filled with an electrically conductive material.
摘要翻译：一种制造贯通基板通孔结构的方法。该方法包括提供具有前侧和相对背面的基板。在基板的前侧形成贯通基板通路孔。贯通基板通孔开口不穿透基板背面的外表面。贯通基板通孔开口填充有固体填充材料。从衬底的背面的外表面去除衬底的部分，从而露出填充材料。暴露的填充材料的至少部分被去除以形成穿过衬底的整个厚度的背面贯穿衬底通孔开口。背面贯通基板通孔开口填充有导电材料。

17. 发明授权

US06313021B1 PMOS device having a layered silicon gate for improved silicide integrity and enhanced boron penetration resistance 有权
标题翻译： PMOS器件具有用于改善硅化物完整性和增强的硼渗透电阻的层状硅栅极
公开(公告)号：US06313021B1
公开(公告)日：2001-11-06
申请号：US09416491
申请日：1999-10-12
申请人： Sailesh M. Merchant , Joseph R. Radosevich , Pradip K. Roy
发明人： Sailesh M. Merchant , Joseph R. Radosevich , Pradip K. Roy
IPC分类号： H01L213205
CPC分类号： H01L21/28035 , H01L21/28044 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4933 , H01L29/4941
摘要： The present invention provides a process for forming a sub-micron p-type metal oxide semiconductor (PMOS) structure on a semiconductor substrate. The process includes forming a gate oxide on the semiconductor substrate, forming a gate layer on the gate oxide by depositing a first gate layer on the gate oxide at a first deposition rate and depositing a second gate layer on the first layer at a second deposition rate to provide an improved stress accommodation within the gate structure. The process further includes forming a silicide dopant barrier on the gate. Due to the presence of the improved stress accommodation in the gate, the integrity of the silicide dopant barrier is substantially enhanced. This increased silicide integrity prevents significant damage to the silicide dopant barrier layer during subsequent fabrication processes. As such, the dopant barrier is able to provide the intended degree of resistance to dopant penetration, for example boron, during the formation of source and drain regions adjacent the gate structure.
摘要翻译：本发明提供了一种在半导体衬底上形成亚微米p型金属氧化物半导体（PMOS）结构的方法。该工艺包括在半导体衬底上形成栅极氧化物，通过以第一沉积速率沉积栅极氧化物上的第一栅极层，以栅极氧化物形成栅极层，并以第二沉积速率在第一层上沉积第二栅极层以在门结构内提供改进的应力调节。该工艺还包括在栅极上形成硅化物掺杂剂阻挡层。由于在栅极中存在改善的应力调节，硅化物掺杂剂势垒的完整性显着增强。这种增加的硅化物完整性防止在随后的制造工艺期间对硅化物掺杂剂阻挡层的显着损坏。因此，在形成与栅极结构相邻的源极和漏极区域期间，掺杂物势垒能够提供对掺杂剂穿透（例如硼）的预期程度的阻抗。

18. 发明授权

US6028359A Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture therefor 失效
标题翻译：具有触点和通孔中的无定形硅化物层的集成电路及其制造方法
公开(公告)号：US6028359A
公开(公告)日：2000-02-22
申请号：US73556
申请日：1998-05-06
申请人： Sailesh M. Merchant , Daniel J. Vitkavage , Susan C. Vitkavage
发明人： Sailesh M. Merchant , Daniel J. Vitkavage , Susan C. Vitkavage
IPC分类号： H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76846 , H01L21/28518 , H01L21/32053 , H01L21/76843 , H01L21/76877
摘要： An integrated circuit, a contact and a method of manufacture therefor. The integrated circuit has a silicon substrate with a recess formed therein that provides an environment within which the contact is formed. The contact includes: (1) an adhesion layer deposited on an inner surface of the recess, (2) an amorphous layer, deposited over the adhesion layer within the recess and (3) a central plug, composed of a conductive material, deposited at least partially within the recess, the silicide layer being amorphous to prevent the conductive material from passing through the amorphous silicide layer to contact the adhesion layer thereby to prevent junction leakage.
摘要翻译：集成电路，触点及其制造方法。集成电路具有形成在其中形成有凹部的硅衬底，其提供形成触点的环境。接触包括：（1）沉积在凹陷内表面上的粘合层，（2）沉积在凹部内的粘合层上的非晶层，和（3）由导电材料组成的中心塞，其沉积在至少部分地在所述凹部内，所述硅化物层是无定形的，以防止所述导电材料穿过所述非晶硅化物层与所述粘合层接触从而防止结漏电。

19. 发明授权

US5858873A Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereof 失效
标题翻译：在触点和通孔中具有无定形硅化物层的集成电路及其制造方法
公开(公告)号：US5858873A
公开(公告)日：1999-01-12
申请号：US816185
申请日：1997-03-12
申请人： Susan C. Vitkavage , Daniel J. Vitkavage , Sailesh M. Merchant
发明人： Susan C. Vitkavage , Daniel J. Vitkavage , Sailesh M. Merchant
IPC分类号： H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76846 , H01L21/28518 , H01L21/32053 , H01L21/76843 , H01L21/76877
摘要： An integrated circuit, a contact and a method of manufacture therefor. The integrated circuit has a silicon substrate with a recess formed therein that provides an environment within which the contact is formed. The contact includes: (1) an adhesion layer deposited on an inner surface of the recess, (2) an amorphous layer, deposited over the adhesion layer within the recess and (3) a central plug, composed of a conductive material, deposited at least partially within the recess, the silicide layer being amorphous to prevent the conductive material from passing through the amorphous silicide layer to contact the adhesion layer thereby to prevent junction leakage.
摘要翻译：集成电路，触点及其制造方法。集成电路具有形成在其中形成有凹部的硅衬底，其提供形成触点的环境。接触包括：（1）沉积在凹陷内表面上的粘合层，（2）沉积在凹部内的粘合层上的非晶层，和（3）由导电材料组成的中心塞，其沉积在至少部分地在所述凹部内，所述硅化物层是无定形的，以防止所述导电材料穿过所述非晶硅化物层与所述粘合层接触从而防止结漏电。

20. 发明授权

US5523259A Method of forming metal layers formed as a composite of sub-layers using Ti texture control layer 失效
标题翻译：使用Ti纹理控制层形成作为子层的复合物的金属层的方法
公开(公告)号：US5523259A
公开(公告)日：1996-06-04
申请号：US349649
申请日：1994-12-05
申请人： Sailesh M. Merchant , Arun K. Nanda , Pradip K. Roy
发明人： Sailesh M. Merchant , Arun K. Nanda , Pradip K. Roy
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5329 , H01L23/5226 , H01L2924/0002
摘要： In an integrated circuit, an opening (e.g., via or window) is filled with an Al-based plug which has essentially a orientation and comprises at most three grains. These characteristics are achieved by first depositing a texture control Ti layer having substantially a (002) basal plane orientation followed by at least three Al-based sublayers. The grain sizes and deposition conditions are controlled in such a way that during deposition of the third sublayer, the microstructure of the plug adjusts itself to produce a single grain (or at most three).
摘要翻译：在集成电路中，开口（例如，通孔或窗口）填充有基本上为111°取向且至多包含三个晶粒的Al-基塞。这些特性通过首先沉积具有基本上（002）基面平面取向的纹理控制Ti层，然后是至少三个基于Al的子层来实现。晶粒尺寸和沉积条件被控制为在沉积第三子层期间，插塞的微观结构自身调整以产生单个颗粒（或至多三个）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式