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11. 发明申请

US20050118833A1 Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20050118833A1
公开(公告)日：2005-06-02
申请号：US10998782
申请日：2004-11-30
申请人： Kazumasa Mitsumune , Tsukasa Doi , Yushi Inoue , Kenichirou Abe , Takanori Sonoda
发明人： Kazumasa Mitsumune , Tsukasa Doi , Yushi Inoue , Kenichirou Abe , Takanori Sonoda
IPC分类号： H01L23/522 , H01L21/31 , H01L21/314 , H01L21/318 , H01L21/768 , H01L21/469
CPC分类号： H01L21/02129 , H01L21/0217 , H01L21/02274 , H01L21/3144 , H01L21/3145 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76837
摘要： It is an object of the present invention to provide a method for manufacturing a semiconductor device suppressing the occurrence of voids in an insulating film. A method for manufacturing a semiconductor device according to the present invention comprises the steps of: (1) forming an insulating film 11 composed of a thin silicon nitride film on a semiconductor substrate 1 having at least a necessary element and a recessed part 6 so as to cover the recessed part 6; (2) modifying the surface of the insulating film 11; and (3) forming a BPSG film 15 as an interlayer insulation film on the insulating film. The occurrence of voids in the interlayer insulation film 15 is suppressed by the process for modifying the surface.
摘要翻译：本发明的目的是提供一种制造半导体器件的方法，该半导体器件抑制绝缘膜中空隙的发生。根据本发明的制造半导体器件的方法包括以下步骤：（1）在具有至少必需元件的半导体衬底1上形成由氮化硅薄膜构成的绝缘膜11，以及凹入部分6，以便覆盖凹部6; （2）改性绝缘膜11的表面; 和（3）在绝缘膜上形成作为层间绝缘膜的BPSG膜15。通过改变表面的方法来抑制层间绝缘膜15中的空隙的发生。

12. 发明授权

US06187648B1 Method of forming a device isolation region 失效
标题翻译：形成器件隔离区域的方法
公开(公告)号：US06187648B1
公开(公告)日：2001-02-13
申请号：US09270755
申请日：1999-03-17
申请人： Tsukasa Doi , Shigeo Ohnishi , Katsuji Iguchi , Naoyuki Shinmura
发明人： Tsukasa Doi , Shigeo Ohnishi , Katsuji Iguchi , Naoyuki Shinmura
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method of forming a device isolation region includes the steps of: forming a first dielectric film and an oxidation-resistant deposition film successively on a semiconductor substrate; forming a trench groove in the semiconductor substrate by successively processing the oxidation-resistant deposition film, the first dielectric film and the semiconductor substrate by anisotropic etching; forming a second dielectric film to cover at least an inner surface of the trench groove; depositing a third dielectric film in the trench groove so that the thickness of the third dielectric film buried in the trench groove is larger than a depth of the trench groove; planarizing a surface of the third dielectric film and an upper surface of the trench groove; and removing the oxidation-resistant deposition film and the first dielectric film to form the device isolation region, wherein a thermal treatment of the entire substrate is carried out to densify the third dielectric film and to oxidize an interface between the second dielectric film and the semiconductor substrate.
摘要翻译：形成器件隔离区域的方法包括以下步骤：在半导体衬底上依次形成第一电介质膜和抗氧化淀积膜; 通过各向异性腐蚀对所述耐氧化沉积膜，所述第一电介质膜和所述半导体衬底进行连续处理，在所述半导体衬底中形成沟槽; 形成第二电介质膜以覆盖所述沟槽的至少内表面; 在沟槽中沉积第三电介质膜，使得埋在沟槽中的第三电介质膜的厚度大于沟槽的深度; 平面化第三电介质膜的表面和沟槽的上表面; 以及去除所述抗氧化沉积膜和所述第一电介质膜以形成所述器件隔离区域，其中执行整个衬底的热处理以使所述第三电介质膜致密化并氧化所述第二电介质膜和所述半导体之间的界面基质。

13. 发明授权

US5241205A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5241205A
公开(公告)日：1993-08-31
申请号：US953197
申请日：1992-09-29
申请人： Shin Shimizu , Katsuji Iguchi , Seizo Kakimoto , Tsukasa Doi
发明人： Shin Shimizu , Katsuji Iguchi , Seizo Kakimoto , Tsukasa Doi
IPC分类号： H01L27/108
CPC分类号： H01L27/10808
摘要： A semiconductor memory device is provided which includes a plurality of memory cells, each of which includes: an active region having an MOS transistor formed in the surface portion of a semiconductor substrate; a gate electrode formed on the substrate for the MOS transistor so as to divide the active region into a source-side active region with a storage contact and a drain-side active region with a bit contact, the portion of the active region which is positioned under the gate electrode functioning as a channel region for the MOS transistor; a first impurity-implanted region formed in a portion of the source-side active region so as to overlap with part of the storage contact and the gate electrode, the portion of the source-side active region which overlaps with the first impurity-implanted region functioning as a source region for the MOS transistor; and a second impurity-implanted region formed in a portion of the drain-side active region so as to overlap with at least one part of the bit contact and the gate electrode, the portion of the drain-side active region which overlaps with the second impurity-implanted region functioning as a drain region for the MOS transistor.
摘要翻译：提供了一种半导体存储器件，其包括多个存储单元，每个存储单元包括：形成在半导体衬底的表面部分中的MOS晶体管的有源区; 形成在所述MOS晶体管的所述基板上的栅电极，以将所述有源区域分为具有位触点的存储触点和漏极侧有源区域的源极侧有源区域，所述有源区域的所述部分位于在作为MOS晶体管的沟道区域的栅电极下方; 形成在所述源侧有源区的一部分中以与所述存储接触和所述栅电极的一部分重叠的第一杂质注入区，所述源侧有源区的与所述第一杂质注入区重叠的部分用作MOS晶体管的源极区域; 以及第二杂质注入区，形成在所述漏极侧有源区的一部分中以与所述位接触和所述栅电极的至少一部分重叠，所述漏极侧有源区的与所述第二杂质注入区重叠的部分杂质注入区用作MOS晶体管的漏极区。

14. 外观设计

USD689448S1 Light emitting diode 有权
公开(公告)号：USD689448S1
公开(公告)日：2013-09-10
申请号：US29421405
申请日：2012-07-19
申请人： Mitsunobu Kimura , Tsukasa Doi , Yufeng Weng
设计人： Mitsunobu Kimura , Tsukasa Doi , Yufeng Weng

15. 发明授权

US07402513B2 Method for forming interlayer insulation film 有权
标题翻译：形成层间绝缘膜的方法
公开(公告)号：US07402513B2
公开(公告)日：2008-07-22
申请号：US11034616
申请日：2005-01-12
申请人： Takanori Sonoda , Kazumasa Mitsumune , Kenichiroh Abe , Yushi Inoue , Tsukasa Doi
发明人： Takanori Sonoda , Kazumasa Mitsumune , Kenichiroh Abe , Yushi Inoue , Tsukasa Doi
IPC分类号： H01L21/461 , H01L21/4763 , H01L21/469
CPC分类号： H01L21/0217 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/02318 , H01L21/3143 , H01L21/31625 , H01L21/3185 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76837
摘要： It is an object of the present invention to provide a method for forming an interlayer insulation film suppressing the occurrence of voids in the interlayer insulation film.A method for forming an interlayer insulation film of the present invention, comprising the steps of: (1) forming an etching stopper film of a silicon nitride film on an entire surface including a step part on a semiconductor substrate having the step part with an aspect ratio of ≧3; (2) forming an interlayer insulation film of an impurity-doped silicate film on the silicon nitride film; and (3) performing reflow of the interlayer insulation film by a heat treatment, wherein the formation of the silicon nitride film is controlled such that the N—H bond density of the silicon nitride film is 1.0×1022 pieces/cm3 or less.According to the method for forming the interlayer insulation film of the present invention, the occurrence of the voids can be suppressed in the interlayer insulation film even if the aspect ratio of the step part formed on the semiconductor substrate is 3 or more. Also, the damage applied to the semiconductor device by reflow can be reduced.
摘要翻译：本发明的目的是提供一种形成层间绝缘膜的方法，该层间绝缘膜抑制层间绝缘膜中空隙的发生。一种形成本发明的层间绝缘膜的方法，包括以下步骤：（1）在具有该步骤部分的半导体衬底上的包括台阶部分的整个表面上形成氮化硅膜的蚀刻阻挡膜，该半导体衬底具有一个方面比值> = 3; （2）在氮化硅膜上形成杂质掺杂硅酸盐膜的层间绝缘膜; 和（3）通过热处理进行层间绝缘膜的回流，其中控制氮化硅膜的形成，使得氮化硅膜的NH键密度为1.0×10 22个/ cm 3以下。根据本发明的层间绝缘膜的形成方法，即使形成在半导体基板上的台阶部的纵横比为3以上，也能够抑制层间绝缘膜的空隙的发生。此外，可以减少通过回流施加到半导体器件的损坏。

16. 发明申请

US20050159015A1 Method for forming interlayer insulation film 有权
标题翻译：形成层间绝缘膜的方法
公开(公告)号：US20050159015A1
公开(公告)日：2005-07-21
申请号：US11034616
申请日：2005-01-12
申请人： Takanori Sonoda , Kazumasa Mitsumune , Kenichiroh Abe , Yushi Inoue , Tsukasa Doi
发明人： Takanori Sonoda , Kazumasa Mitsumune , Kenichiroh Abe , Yushi Inoue , Tsukasa Doi
IPC分类号： C23C16/34 , H01L21/28 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/522 , H01L21/4763 , H01L21/469
CPC分类号： H01L21/0217 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/02318 , H01L21/3143 , H01L21/31625 , H01L21/3185 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76837
摘要： It is an object of the present invention to provide a method for forming an interlayer insulation film suppressing the occurrence of voids in the interlayer insulation film. A method for forming an interlayer insulation film of the present invention, comprising the steps of: (1) forming an etching stopper film of a silicon nitride film on an entire surface including a step part on a semiconductor substrate having the step part with an aspect ratio of ≧3; (2) forming an interlayer insulation film of an impurity-doped silicate film on the silicon nitride film; and (3) performing reflow of the interlayer insulation film by a heat treatment, wherein the formation of the silicon nitride film is controlled such that the N—H bond density of the silicon nitride film is 1.0×1022 pieces/cm3 or less. According to the method for forming the interlayer insulation film of the present invention, the occurrence of the voids can be suppressed in the interlayer insulation film even if the aspect ratio of the step part formed on the semiconductor substrate is 3 or more. Also, the damage applied to the semiconductor device by reflow can be reduced.
摘要翻译：本发明的目的是提供一种形成层间绝缘膜的方法，该层间绝缘膜抑制层间绝缘膜中空隙的发生。一种形成本发明的层间绝缘膜的方法，包括以下步骤：（1）在具有该步骤部分的半导体衬底上的包括台阶部分的整个表面上形成氮化硅膜的蚀刻阻挡膜，该半导体衬底具有一个方面比值> = 3; （2）在氮化硅膜上形成杂质掺杂硅酸盐膜的层间绝缘膜; 和（3）通过热处理进行层间绝缘膜的回流，其中控制氮化硅膜的形成，使得氮化硅膜的NH键密度为1.0×10 22个/ cm 3以下。根据本发明的层间绝缘膜的形成方法，即使形成在半导体基板上的台阶部的纵横比为3以上，也能够抑制层间绝缘膜的空隙的发生。此外，可以减少通过回流施加到半导体器件的损坏。

17. 发明授权

US5744394A Method for fabricating a semiconductor device having copper layer 失效
标题翻译：具有铜层的半导体器件的制造方法
公开(公告)号：US5744394A
公开(公告)日：1998-04-28
申请号：US839025
申请日：1997-04-23
申请人： Katsuji Iguchi , Tsukasa Doi , Masanori Murakami , Takeo Oku
发明人： Katsuji Iguchi , Tsukasa Doi , Masanori Murakami , Takeo Oku
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8246 , H01L23/522 , H01L27/112 , H01L29/45
CPC分类号： H01L27/11293 , H01L29/456
摘要： A semiconductor device comprises a plurality of transistors A semiconductor device comprising a plurality of transistors formed on a semiconductor substrate and a metal interconnection layer connected to at least one of the transistors, wherein the metal interconnection layer is composed of a single layer or multi layers, the single layer or at least one layer of the multi layers being formed of copper or a copper alloy, and is connected to at least one transistor wholly or partially through a barrier layer; and at least one of the transistor is controlled on its threshold voltage by a selective ion implantation after formation of the metal interconnection layer.
摘要翻译：半导体器件包括多个晶体管，包括形成在半导体衬底上的多个晶体管和连接到至少一个晶体管的金属互连层的半导体器件，其中金属互连层由单层或多层组成，单层或多层的至少一层由铜或铜合金形成，并且通过阻挡层全部或部分连接至至少一个晶体管; 并且在形成金属互连层之后，通过选择性离子注入将晶体管中的至少一个控制在其阈值电压上。

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