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11. 发明专利

JP2011113997A Semiconductor device, and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011113997A
公开(公告)日：2011-06-09
申请号：JP2009266021
申请日：2009-11-24
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： KATSUNO TAKASHI , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , YAMAMOTO TAKEO , ENDO TAKESHI , FUJIWARA HIROKAZU , KONISHI MASAKI
IPC分类号： H01L29/41 , H01L21/28 , H01L21/329 , H01L21/336 , H01L29/12 , H01L29/417 , H01L29/47 , H01L29/78 , H01L29/861 , H01L29/872
CPC分类号： H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a technology for manufacturing a semiconductor element that forms multiple trenches for forming electrodes on a back-surface layer of a silicon carbide substrate inexpensively.
SOLUTION: Multiple etch pits 24 are formed by wet etching in response to parts where displacement exist on a back-surface layer of the silicon carbide substrate 13. A cathode electrode 32 that ohmicly contacts with the silicon carbide substrate is formed by a sputtering method. Multiple p-layers 16 are formed on a front-surface layer of the silicon carbide substrate 13 and then an anode electrode 34 is formed by a sputtering method. Thus, a junction barrier Schottky diode is formed.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供一种用于制造半导体元件的技术，该半导体元件形成用于在碳化硅衬底的背表面层上形成电极的多个沟槽。解决方案：响应于在碳化硅衬底13的背面层上存在位移的部分，通过湿蚀刻形成多个蚀刻凹坑24.与碳化硅衬底欧姆接触的阴极32形成为溅射法。在碳化硅衬底13的前表面层上形成多个p层16，然后通过溅射法形成阳极34。因此，形成结屏障肖特基二极管。版权所有（C）2011，JPO＆INPIT

12. 发明专利

JP2014053595A Silicon carbide semiconductor device and manufacturing method of the same 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2014053595A
公开(公告)日：2014-03-20
申请号：JP2013156393
申请日：2013-07-29
申请人： Denso Corp , 株式会社デンソー , Toyota Motor Corp , トヨタ自動車株式会社 , Toyota Central R&D Labs Inc , 株式会社豊田中央研究所
发明人： MIYAHARA SHINICHIRO , YAMAMOTO TOSHIMASA , MORIMOTO JUN , SOEJIMA SHIGEMASA , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/316 , H01L21/336 , H01L29/12
CPC分类号： H01L29/66734 , H01L21/049 , H01L21/28158 , H01L21/30604 , H01L29/045 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/4238 , H01L29/66068 , H01L29/7397 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To inhibit the occurrence of leakage current to achieve an SiC semiconductor device with a gate oxide film having higher reliability.SOLUTION: In composition of a vertical MOSFET having a trench gate structure 9 by using an ntype substrate 1 and the like having an off angle to a (0001) plane or a (000-1) plane, a gate oxide film 7 is formed after forming a trench 6 without performing a sacrificial oxidation process. By doing this, the vertical MOSFET needs not be influenced by the sacrificial oxidation process and can inhibit the partial occurrence of leakage current in the trench gate structure 9 thereby to enable achievement of an SiC semiconductor device with a gate oxide film 7 having higher reliability.
摘要翻译：要解决的问题：为了抑制漏电流的发生，实现具有较高可靠性的栅极氧化膜的SiC半导体器件。解决方案：通过使用n型衬底1等具有沟槽栅极结构9的垂直MOSFET的组成与（0001）面或（000-1）面成偏角时，在不进行牺牲氧化处理的状态下，在形成沟槽6之后形成栅极氧化膜7。通过这样做，垂直MOSFET不需要受牺牲氧化处理的影响，并且可以抑制沟槽栅极结构9中的部分泄漏电流的发生，从而能够实现具有更高可靠性的栅极氧化膜7的SiC半导体器件。

13. 发明专利

JP2014017469A Silicon carbide semiconductor device and manufacturing method of the same 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2014017469A
公开(公告)日：2014-01-30
申请号：JP2013049229
申请日：2013-03-12
申请人： Denso Corp , 株式会社デンソー , Toyota Motor Corp , トヨタ自動車株式会社
发明人： TAKEUCHI YUICHI , SUZUKI NAOHIRO , SUGIMOTO MASAHIRO , TAKATANI HIDESHI , SOENO AKITAKA , MORIMOTO JUN , SOEJIMA SHIGEMASA , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L27/04 , H01L29/06 , H01L29/12 , H01L29/423 , H01L29/47 , H01L29/49 , H01L29/872
CPC分类号： H01L29/7811 , H01L21/046 , H01L21/0475 , H01L21/30604 , H01L21/308 , H01L21/761 , H01L21/8213 , H01L29/0615 , H01L29/063 , H01L29/0634 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/157 , H01L29/158 , H01L29/1608 , H01L29/41766 , H01L29/4236 , H01L29/66068 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7813 , H01L29/861 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To achieve both of reduction in on-resistance and fracture prevention of a gate insulation film.SOLUTION: A silicon carbide semiconductor device comprises a p-type region 5 having a low-concentration region 5b and a high-concentration region 5c in such a way as to be buried in trenches 5a formed in a cell region. The low-concentration region 5b composes a p type column, and the high-concentration region 5c composes a ptype deep layer. With this configuration, reduction in on-resistance can be achieved because the p type column by the low-concentration region 5c and an n type column by an n type drift layer 2 can constitute an SJ (Super Junction) structure. In addition, an electric field applied to a gate insulation film 8 can be absorbed because drain potential can be blocked by the ptype deep layer by the high-concentration region 5c during off-state thereby to enable fracture prevention of the gate insulation film 8. Accordingly, the SiC semiconductor device which can achieve both of reduction in on-resistance and fracture prevention of the gate insulation film 8 can be achieved.
摘要翻译：要解决的问题：实现栅极绝缘膜的导通电阻和断裂防止的降低。解决方案：碳化硅半导体器件包括具有低浓度区域5b和高浓度区域的p型区域5 5c以这样的方式被埋在形成在单元区域中的沟槽5a中。低浓度区域5b构成p型列，高浓度区域5c构成p型深层。通过这种结构，由于低浓度区域5c的p型列和n型漂移层2的n型列可以构成SJ（超级结）结构，所以可以实现导通电阻的降低。此外，由于在断开状态下可能被高浓度区域5c的p型深层阻挡漏极电位，所以可以吸收施加到栅极绝缘膜8的电场，从而能够防止栅极绝缘膜8的断裂。因此，可以实现能够实现栅极绝缘膜8的导通电阻降低和断裂防止两者的SiC半导体装置。

14. 发明专利

JP2013229382A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2013229382A
公开(公告)日：2013-11-07
申请号：JP2012098912
申请日：2012-04-24
申请人： Toyota Motor Corp , トヨタ自動車株式会社 , Denso Corp , 株式会社デンソー
发明人： SUGIMOTO MASAHIRO , SOEJIMA SHIGEMASA , YAMAMOTO KENSAKU
IPC分类号： H01L29/78 , H01L21/28 , H01L29/12 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a technique that can improve the breakdown-voltage performance of a semiconductor device.SOLUTION: A semiconductor device includes a first semiconductor region composed of a first-conductivity-type semiconductor, a second semiconductor region composed of a second-conductivity-type semiconductor, and a third semiconductor region composed of the first-conductivity-type semiconductor. The semiconductor device also includes a gate electrode having a part opposed to the first semiconductor region via an insulating film. In the semiconductor device, the gate electrode is composed of the second-conductivity-type semiconductor. The gate electrode has, at its portion, a first region being in contact with the insulating film of a part being in contact with the first semiconductor region. In the gate electrode, the second-conductivity-type impurity concentration of the first region is lower than the value in which the entire second-conductivity-type impurity concentrations of the gate electrode are averaged.
摘要翻译：要解决的问题：提供可以提高半导体器件的击穿电压性能的技术。解决方案：半导体器件包括由第一导电型半导体构成的第一半导体区域，由第二导电型半导体构成的第二半导体区域导电型半导体，以及由第一导电型半导体构成的第三半导体区域。半导体器件还包括通过绝缘膜具有与第一半导体区域相对的部分的栅电极。在半导体装置中，栅电极由第二导电型半导体构成。栅电极在其部分处具有与与第一半导体区域接触的部分的绝缘膜接触的第一区域。在栅电极中，第一区域的第二导电型杂质浓度低于栅电极的第二导电型杂质浓度的平均值的值。

15. 发明专利

JP2013214660A Silicon carbide semiconductor device and manufacturing method of the same 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2013214660A
公开(公告)日：2013-10-17
申请号：JP2012084912
申请日：2012-04-03
申请人： Denso Corp , 株式会社デンソー , Toyota Motor Corp , トヨタ自動車株式会社
发明人： WATANABE HIROKI , YAMAMOTO KENSAKU , MORIMOTO JUN , NARUOKA HIDEKI , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA
IPC分类号： H01L29/78 , H01L21/20 , H01L21/324 , H01L21/336 , H01L29/12
摘要： PROBLEM TO BE SOLVED: To reduce drain leakage due to point defects.SOLUTION: In a silicon carbide semiconductor device, a depth X of a peak position in a distribution of the number of point defects along a depth direction from a surface of a semiconductor substrate and a PN junction position Y formed by an ntype drift layer 2 and a p type base region 3 from the surface satisfy a relationship represented as X
摘要翻译：要解决的问题：减少由于点缺陷引起的漏极泄漏。解决方案：在碳化硅半导体器件中，从半导体衬底的表面沿深度方向的点缺陷数的分布中的峰值位置的深度X 并且从表面形成的n型漂移层2和ap型基极区域3形成的PN结位置Y满足表示为X

16. 发明专利

JP2013214659A Silicon carbide semiconductor device manufacturing method 有权
标题翻译：硅碳化硅半导体器件制造方法
公开(公告)号：JP2013214659A
公开(公告)日：2013-10-17
申请号：JP2012084911
申请日：2012-04-03
申请人： Denso Corp , 株式会社デンソー , Toyota Motor Corp , トヨタ自動車株式会社
发明人： MORINO TOMOO , MIZUNO SHOJI , KONISHI MASAKI , SOEJIMA SHIGEMASA
IPC分类号： H01L21/28 , H01L29/47 , H01L29/872
CPC分类号： H01L29/872
摘要： PROBLEM TO BE SOLVED: To expose whether element breakage occurs in the future in a manufacturing stage.SOLUTION: A silicon carbide semiconductor device manufacturing method comprises: performing annealing after formation of an electrode 8 for bonding at a temperature where a barrier height of the electrode 8 for bonding becomes lower than that of a Schottky electrode 4; and performing annealing also after formation of a surface electrode 9, at a temperature where a component of the surface electrode 9 causes migration. By doing this, whether element breakage occurs in the future can be exposed in a manufacturing stage. In a process of determining non-defective or defective, it becomes possible to remove a defective and only select non-defective chip.
摘要翻译：要解决的问题：是否在制造阶段揭示将来是否发生元件断裂。解决方案：碳化硅半导体器件的制造方法包括：在电极的势垒高度的温度下形成用于接合的电极8之后进行退火 8相比低于肖特基电极4; 并且在表面电极9的成分引起迁移的温度下，在形成表面电极9之后也进行退火。通过这样做，未来元件破损是否可以在制造阶段暴露出来。在确定无缺陷或缺陷的过程中，可以去除有缺陷且仅选择无缺陷芯片。

17. 发明专利

JP2013012590A Silicon carbide semiconductor device 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2013012590A
公开(公告)日：2013-01-17
申请号：JP2011144320
申请日：2011-06-29
申请人： Denso Corp , 株式会社デンソー , Toyota Motor Corp , トヨタ自動車株式会社 , Toyota Central R&D Labs Inc , 株式会社豊田中央研究所
发明人： MIYAHARA SHINICHIRO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0865 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/7825 , H01L29/7827
摘要： PROBLEM TO BE SOLVED: To obtain a high channel mobility by bringing the side surface of a trench, in which a channel is formed, close to the (11-20) plane or the (1-100) plane capable of increasing the channel mobility.SOLUTION: An nsource region 5 is formed so as to come into contact with one side surface out of both side surfaces of a trench 7, i.e. the side surface which forms an angle of 90° or an angle close to it with respect to the (0001) plane, so that a channel is formed in only one of both side surfaces of the trench 7. Since the channel can be formed only in the side surface where a high channel mobility is formed out of both side surfaces of the trench 7, a high channel mobility can be obtained.
摘要翻译：要解决的问题：为了通过使形成沟道的沟槽的侧表面靠近能够增加的（11-20）面或（1-100）面来获得高沟道迁移率渠道流动性。源极区域5形成为与沟槽7的两个侧表面中的一个侧表面接触，即侧表面相对于（0001）面形成90°的角度或与其接近的角度，使得沟槽仅形成在沟槽7的两个侧表面中的一个中。由于沟道仅可以形成在侧表面其中在沟槽7的两个侧表面形成高沟道迁移率，可以获得高沟道迁移率。版权所有（C）2013，JPO＆INPIT

18. 发明专利

JP2012169384A Silicon carbide semiconductor device and method of manufacturing the same 审中-公开
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2012169384A
公开(公告)日：2012-09-06
申请号：JP2011027995
申请日：2011-02-11
申请人： Denso Corp , Toyota Motor Corp , Toyota Central R&D Labs Inc , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： YAMAMOTO KENSAKU , NOBORIO MASATO , MATSUKI HIDEO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , MORIMOTO JUN , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12 , H01L29/739
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/66348 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To reduce the on-resistance when a deep layer is formed so as to intersect a trench configuring a trench gate structure.SOLUTION: A p-type deep layer 10 has structure where the upper part is narrower than the lower part. For example, the p-type deep layer 10 is constituted by a lower layer region 10a and an upper layer region 10b, and the upper layer region 10b is made narrower than the lower layer region 10a. Consequently, when a channel is formed by applying a gate voltage to a gate electrode 9 during on time on the upper periphery of the p-type deep layer 10, the channel width can be widened. When compared with a case where the width of the p-type deep layer 10 is fixed entirely, i.e. fixed to the same width as that of the lower layer region 10a, a JFET region can be widened and the JFET resistance can be reduced. The on-resistance can thereby be reduced.
摘要翻译：要解决的问题：当形成深层以与构成沟槽栅极结构的沟槽交叉时，降低导通电阻。解决方案：p型深层10具有其上部比下部更窄的结构。例如，p型深层10由下层区域10a和上层区域10b构成，上层区域10b比下层区域10a窄。因此，当在p型深层10的上部周边上的栅极电极9上施加栅极电压而形成沟道时，可以扩大通道宽度。当与p型深层10的宽度完全固定即固定为与下层区域10a的宽度相同的宽度的情况相比，可以加宽JFET区域并且可以减小JFET电阻。因此可以降低导通电阻。版权所有（C）2012，JPO＆INPIT

19. 发明专利

JP2012116732A Method of manufacturing silicon carbide single crystal 有权
标题翻译：制造单晶碳化硅的方法
公开(公告)号：JP2012116732A
公开(公告)日：2012-06-21
申请号：JP2010270295
申请日：2010-12-03
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： WATANABE HIROKI , KITO YASUO , FURUKAWA TAIJI , YAMAMOTO KENSAKU , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI
IPC分类号： C30B29/36 , C30B25/20 , H01L21/205
CPC分类号： H01L21/0262 , C30B25/186 , C30B29/36 , H01L21/02378 , H01L21/0243 , H01L21/02529 , H01L21/02658 , H01L21/046 , H01L21/0475 , H01L29/04
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an SiC single crystal capable of reducing threading dislocations while suppressing transfer of polymorphism and dislocation without performing sequential lamination of p-layers and n-layers.SOLUTION: A very deep etch pit 1b is formed in the position corresponding to a leak portion by performing molten KOH etching and the like after Al ion implantation and activation annealing, based on findings that a dislocation causing leak such as a drain leak of a vertical MOSFET is a threading screw dislocation. When an SiC growth layer 4 is epitaxially grown on the surface of the etch pit 1b in such a condition that portions grown in the side wall parts of the etch pit 1b are brought into contact mutually, the dislocation is prevented from being transferred to the SiC growth layer 4. In this way, the SiC growth layer 4 having the surface including no threading screw dislocation 1a can be obtained. Therefore, without performing sequential lamination of p-layers and n-layers, the SiC single crystal capable of reducing threading screw dislocations can be produced while suppressing transfer of polymorphism and dislocation.
摘要翻译：要解决的问题：提供一种能够在不进行p层和n层的顺序层压的同时抑制多晶型转移和位错的同时能够减少穿透位错的SiC单晶的制造方法。解决方案：通过在Al离子注入和活化退火之后进行熔融KOH蚀刻等形成在与泄漏部分相对应的位置中的非常深的蚀刻坑1b，基于发现泄漏如泄漏泄漏的位错的垂直MOSFET是螺纹螺钉错位。当在蚀刻凹坑1b的表面上外延生长SiC生长层4，使得在蚀刻坑1b的侧壁部分中生长的部分相互接触的情况下，防止位错转移到SiC 以这种方式，可以获得具有不包括螺纹螺纹位错1a的表面的SiC生长层4。因此，在不进行p层和n层的顺序层叠的情况下，能够抑制多晶型和位错的转移而能够减少螺纹位错的SiC单晶。版权所有（C）2012，JPO＆INPIT

20. 发明专利

JP2012069797A Insulated gate transistor 审中-公开
标题翻译：绝缘栅晶体管
公开(公告)号：JP2012069797A
公开(公告)日：2012-04-05
申请号：JP2010214240
申请日：2010-09-24
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , ISHIKAWA TAKESHI , SOEJIMA SHIGEMASA , WATANABE YUKIHIKO , SUZUKI MASAHIRO , MATSUKI HIDEO
IPC分类号： H01L29/78 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide an insulated gate transistor, having a trench gate electrode with a high breakdown voltage characteristic, hardly producing a manufacturing error in the breakdown voltage characteristic.SOLUTION: The insulated gate transistor includes: a first region of first conductive type, formed in the range facing the upper surface of a semiconductor layer and connected to a first electrode; a second region of second conductive type, formed on the lower side of the first region; a third region of first conductive type formed on the lower side of the second region; a pair of fourth regions of second conductive type, connected to the first electrode; and a trench gate electrode. Each of the pair of fourth regions is formed on each side of a trench to sandwich the center of the trench. Each of the fourth regions has a vertical region extending to a position deeper than the lower end of an insulating film in the third region, and a horizontal region extending to the center side of the trench from the vertical region in the third region, in the position deeper than the lower end of the insulating film.
摘要翻译：解决的问题：为了提供具有高击穿电压特性的沟槽栅电极的绝缘栅晶体管，几乎不产生击穿电压特性的制造误差。解决方案：绝缘栅晶体管包括：第一导电类型的第一区域，形成在面向半导体层的上表面并连接到第一电极的范围内; 第二导电类型的第二区域，形成在第一区域的下侧; 形成在所述第二区域的下侧的第一导电类型的第三区域; 连接到第一电极的一对第二导电类型的第四区域; 和沟槽栅电极。一对第四区域中的每一个形成在沟槽的每一侧以夹住沟槽的中心。每个第四区域具有延伸到比第三区域中的绝缘膜的下端更深的位置的垂直区域，以及从第三区域中的垂直区域延伸到沟槽的中心侧的水平区域，在位置比绝缘膜的下端深。版权所有（C）2012，JPO＆INPIT

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