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11. 发明授权

US06599830B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US06599830B2
公开(公告)日：2003-07-29
申请号：US10187998
申请日：2002-07-03
申请人： Takeshi Furusawa , Takao Kumihashi , Shuntaro Machida
发明人： Takeshi Furusawa , Takao Kumihashi , Shuntaro Machida
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/02126 , H01L21/02282 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/3122 , H01L21/76802 , H01L21/76807 , H01L21/7681 , H01L21/76811 , H01L21/76813 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.

12. 发明授权

US08513808B2 Semiconductor device having trench-isolated element formation region 有权
标题翻译：具有沟槽隔离元件形成区域的半导体器件
公开(公告)号：US08513808B2
公开(公告)日：2013-08-20
申请号：US13095735
申请日：2011-04-27
申请人： Katsuhiko Hotta , Takeshi Furusawa , Toshikazu Matsui , Takuro Homma
发明人： Katsuhiko Hotta , Takeshi Furusawa , Toshikazu Matsui , Takuro Homma
IPC分类号： H01L23/522 , H01L21/768 , H01L23/525
CPC分类号： H01L24/03 , H01L23/522 , H01L23/53223 , H01L23/585 , H01L24/05 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05096 , H01L2224/05166 , H01L2224/05187 , H01L2224/05554 , H01L2224/05567 , H01L2224/05571 , H01L2224/05624 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01021 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/04941 , H01L2924/1306 , H01L2924/14 , H01L2924/04953 , H01L2924/00014 , H01L2924/00 , H01L2224/05552
摘要： Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M6 used for bonding pads naked, and the inner walls (the side surfaces and the bottom surface) of a slit made to surround the circumference of a guard ring and made in a first passivation film, an insulating film for bonding, and an interlayer dielectric, so as to cause the bottom thereof not to penetrate through a barrier insulating film.
摘要翻译：提供了一种能够提高半导体器件的半导体器件的可靠性的技术，该半导体器件具有在半导体衬底的主表面上形成的狭缝，以便围绕每个元件形成区域。在该技术中，第二钝化膜覆盖开口的侧表面，使得用于接合焊盘的第六层互连M6的上表面裸露，狭缝的内壁（侧表面和底表面）围绕保护环的周围并制成第一钝化膜，用于接合的绝缘膜和层间电介质，以使其底部不穿透阻挡绝缘膜。

13. 发明授权

US07816268B2 Semiconductor device and manufacturing method of semiconductor device 有权
公开(公告)号：US07816268B2
公开(公告)日：2010-10-19
申请号：US12714039
申请日：2010-02-26
申请人： Takeshi Furusawa , Daisuke Kodama , Masahiro Matsumoto , Hiroshi Miyazaki
发明人： Takeshi Furusawa , Daisuke Kodama , Masahiro Matsumoto , Hiroshi Miyazaki
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76805 , H01L21/76844 , H01L21/76877 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen. The predetermined additive element reacts with nitrogen to form a high-resistance part. In addition, the concentration of the predetermined additive element is not more than 0.04 wt %.

14. 发明申请

US20090184424A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090184424A1
公开(公告)日：2009-07-23
申请号：US12350268
申请日：2009-01-08
申请人： Takeshi Furusawa , Takao Kamoshima , Masatsugu Amishiro
发明人： Takeshi Furusawa , Takao Kamoshima , Masatsugu Amishiro
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/535 , H01L22/32 , H01L23/522 , H01L23/562 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/02126 , H01L2224/02166 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05095 , H01L2224/05166 , H01L2224/05187 , H01L2224/05548 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2224/45015 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/20753 , H01L2924/30105 , H01L2924/00 , H01L2224/45099
摘要： The production of a crack in an insulating film under an external terminal of a semiconductor device due to external force applied to the external terminal is suppressed or prevented. Over the principal surface of a semiconductor substrate, there are formed multiple wiring layers. In the fifth wiring layer directly under the uppermost wiring layer of the wiring layers, the following measure is taken: a conductor pattern (fifth wiring, dummy wiring, and plug) is not formed directly under the probe contact area of each bonding pad PD in the uppermost wiring layer. In the fifth wiring layer, conductor patterns (fifth wiring, dummy wirings, and plugs) are formed in the areas other than directly under the probe contact area of each bonding pad in the uppermost wiring layer.
摘要翻译：抑制或防止由于施加到外部端子的外力而在半导体器件的外部端子下的绝缘膜中产生裂纹。在半导体衬底的主表面上形成多个布线层。在配线层的最上层布线层的正下方的第五布线层中，采取以下措施：在每个焊盘PD的探针接触区域的正下方不形成导体图案（第五布线，虚拟布线和插头）最上面的布线层。在第五布线层中，在最上层配线层的各接合焊盘的探针接触区域的正下方的区域形成有导体图案（第五布线，虚拟布线和插头）。

15. 发明申请

US20060055005A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060055005A1
公开(公告)日：2006-03-16
申请号：US11220603
申请日：2005-09-08
申请人： Takeshi Furusawa , Norio Miura , Kinya Goto , Masazumi Matsuura
发明人： Takeshi Furusawa , Norio Miura , Kinya Goto , Masazumi Matsuura
IPC分类号： H01L23/58 , H01L23/52
CPC分类号： H01L23/585 , H01L23/3192 , H01L23/53295 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
摘要翻译：根据本发明的半导体器件是一种半导体器件，其包括相对介电常数小于3.5的低介电常数膜，在平面图中设置有一个或多个密封环，该密封环是闭环形式的防潮壁并且其中至少一个所述密封环包括在芯片角附近以向内突出形式的密封环突出部分。

16. 发明申请

US20110215447A1 SEMICONDUCTOR CHIP WITH SEAL RING AND SACRIFICIAL CORNER PATTERN 有权
标题翻译：半导体芯片与密封圈和阳刚角图案
公开(公告)号：US20110215447A1
公开(公告)日：2011-09-08
申请号：US13112738
申请日：2011-05-20
申请人： Takeshi Furusawa , Norio Miura , Kinya Goto , Masazumi Matsuura
发明人： Takeshi Furusawa , Norio Miura , Kinya Goto , Masazumi Matsuura
IPC分类号： H01L23/58
CPC分类号： H01L23/585 , H01L23/3192 , H01L23/53295 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
摘要翻译：包括相对介电常数小于3.5的低介电常数膜的半导体器件设置有一个或多个密封环，该密封环是在平面图中形成闭环的防潮壁，并且其中至少一个密封件环在芯片角附近包括向内突出形式的密封环突出部。

17. 发明授权

US07700487B2 Semiconductor device and manufacturing method of semiconductor device 有权
标题翻译：半导体器件及半导体器件的制造方法
公开(公告)号：US07700487B2
公开(公告)日：2010-04-20
申请号：US11622767
申请日：2007-01-12
申请人： Takeshi Furusawa , Daisuke Kodama , Masahiro Matsumoto , Hiroshi Miyazaki
发明人： Takeshi Furusawa , Daisuke Kodama , Masahiro Matsumoto , Hiroshi Miyazaki
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/76843 , H01L21/76805 , H01L21/76844 , H01L21/76877 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen. The predetermined additive element reacts with nitrogen to form a high-resistance part. In addition, the concentration of the predetermined additive element is not more than 0.04 wt %.
摘要翻译：为了提供一种半导体器件，其具有在铜合金布线和通孔之间的连接面上形成含有氮的阻挡金属膜的结构，其中可以防止铜合金布线和通孔之间的电阻上升，并且可以防止电阻变化。根据本发明的半导体器件包括第一铜合金布线，通孔和第一阻挡金属膜。第一铜合金布线形成在层间绝缘膜中，并且在主要成分Cu中含有预定的添加元素。通孔形成在层间绝缘膜中并与第一铜合金布线的上表面电连接。第一阻挡金属膜形成为与第一铜合金布线和通孔之间的连接部分中的第一铜合金布线接触并且包含氮。预定的添加元素与氮反应形成高电阻部分。此外，预定添加元素的浓度不大于0.04重量％。

18. 发明申请

US20080230847A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080230847A1
公开(公告)日：2008-09-25
申请号：US12014078
申请日：2008-01-14
申请人： Takeshi Furusawa , Takao Kamoshima , Masatsugu Amishiro , Naohito Suzumura , Shoichi Fukui , Masakazu Okada
发明人： Takeshi Furusawa , Takao Kamoshima , Masatsugu Amishiro , Naohito Suzumura , Shoichi Fukui , Masakazu Okada
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76832 , H01L21/76834 , H01L21/76883
摘要： The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.
摘要翻译：提高了在最低层布线中具有嵌入线的半导体器件的可靠性。在半导体衬底的主表面中，形成MISFET，并且在主表面上形成绝缘膜10,11。在绝缘膜10,11中形成有接触孔，并且插入插头。在插入插头的绝缘膜11上形成绝缘膜14,15,16，并且在绝缘膜14,15,16中形成开口，并且在其中嵌入线。绝缘膜15是在蚀刻绝缘膜16以形成包含硅和碳的开口时的蚀刻停止膜。绝缘膜11具有高的吸湿性，绝缘膜15具有低的耐湿性，然而，通过在其间插入绝缘膜14，使得绝缘膜14具有比Si（硅）原子数更高的Si（硅）原子数绝缘膜11，电阻弱的界面被防止形成。

19. 发明授权

US06777325B2 Semiconductor manufacturing method for low-k insulating film 有权
标题翻译：低k绝缘膜的半导体制造方法
公开(公告)号：US06777325B2
公开(公告)日：2004-08-17
申请号：US10414010
申请日：2003-04-16
申请人： Daisuke Ryuzaki , Takeshi Furusawa
发明人： Daisuke Ryuzaki , Takeshi Furusawa
IPC分类号： H01L214763
CPC分类号： H01L21/76826 , C23C16/0272 , C23C16/401 , H01L21/02126 , H01L21/02131 , H01L21/022 , H01L21/02216 , H01L21/02282 , H01L21/02321 , H01L21/0234 , H01L21/02362 , H01L21/312 , H01L21/3122 , H01L21/3143 , H01L21/3148 , H01L21/31629 , H01L21/31633 , H01L21/3185 , H01L21/76801 , H01L21/76807 , H01L21/76819 , H01L21/76822 , H01L21/76829 , H01L21/76832 , H01L21/76835 , H01L21/7684
摘要： Disclosed is a semiconductor device having a dielectric film of a stacked structure, comprising a low dielectric constant film containing silicon, oxygen and carbon a modified layer for the low dielectric constant film containing silicon, oxygen, carbon and fluorine and a dielectric protection film formed successively on a semiconductor substrate, the semiconductor device being manufactured by applying a plasma treatment using a fluorine-containing gas to the surface of an organic siloxane film to form a modified layer and then forming a dielectric protection film, which can improve the adhesivity with the dielectric protection film without increasing the dielectric constant of the organic siloxane film to prevent delamination.
摘要翻译：公开了具有叠层结构的电介质膜的半导体器件，包括含有硅，氧和碳的低介电常数膜，用于含有硅，氧，碳和氟的低介电常数膜的改性层和相继形成的介电保护膜在半导体衬底上，半导体器件是通过使用含氟气体的等离子体处理施加到有机硅氧烷膜的表面上以形成改性层，然后形成电介质保护膜来制造的，这可以改善与电介质的粘附性保护膜不增加有机硅氧烷膜的介电常数，防止分层。

20. 发明授权

US08963291B2 Semiconductor chip with seal ring and sacrificial corner pattern 有权
标题翻译：半导体芯片具有密封圈和牺牲角图案
公开(公告)号：US08963291B2
公开(公告)日：2015-02-24
申请号：US13112738
申请日：2011-05-20
申请人： Takeshi Furusawa , Noriko Miura , Kinya Goto , Masazumi Matsuura
发明人： Takeshi Furusawa , Noriko Miura , Kinya Goto , Masazumi Matsuura
IPC分类号： H01L21/56
CPC分类号： H01L23/585 , H01L23/3192 , H01L23/53295 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
摘要翻译：包括相对介电常数小于3.5的低介电常数膜的半导体器件设置有一个或多个密封环，该密封环是在平面图中形成闭环的防潮壁，并且其中至少一个密封件环在芯片角附近包括向内突出形式的密封环突出部。

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