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    • 13. 发明申请
    • Processor for performing context switching, a method for performing context switching, a computer program for perform context switching
    • 用于执行上下文切换的处理器,用于执行上下文切换的方法,用于执行上下文切换的计算机程序
    • US20050216708A1
    • 2005-09-29
    • US10972341
    • 2004-10-26
    • Isao Katayama
    • Isao Katayama
    • G06F9/46G06F9/00G06F9/48
    • G06F9/462
    • A processor for performing context switching, including: (a) a register unit configured to include a primary register used in program execution by the processor and a secondary register having a same structure as the primary register; (b) a data storage unit configured to be used as a data storage area in the program execution; (c) a transfer unit configured to include a transfer register used in data transfer between the secondary register and the data storage unit; and (d) an arithmetic unit configured to perform the copy between the primary and secondary registers in a cycle and performs the data transfer between the data storage unit and the secondary register in parallel to instruction execution by the processor when the instruction execution by the processor does not involve memory access to the data storage unit.
    • 一种用于执行上下文切换的处理器,包括:(a)寄存器单元,被配置为包括由处理器在程序执行中使用的主寄存器和具有与主寄存器相同结构的辅助寄存器; (b)数据存储单元,被配置为在程序执行中用作数据存储区域; (c)传送单元,被配置为包括在二次寄存器和数据存储单元之间的数据传送中使用的传送寄存器; 以及(d)算术单元,被配置为在一个周期中执行所述主寄存器和次寄存器之间的复制,并且当所述处理器的指令执行时由所述处理器执行指令执行并且执行所述数据存储单元与所述辅助寄存器之间的数据传送 不涉及对数据存储单元的存储器访问。
    • 19. 发明授权
    • Virtual component having a detachable verification-supporting circuit, a method of verifying the same, and a method of manufacturing an integrated circuit
    • 具有可拆卸验证支持电路的虚拟部件,其验证方法以及集成电路的制造方法
    • US07197731B2
    • 2007-03-27
    • US10105367
    • 2002-03-26
    • Isao Katayama
    • Isao Katayama
    • G06F17/50
    • G06F17/5045G06F17/5022
    • A computer readable medium encoded with a hardware description language describing a virtual component for an integrated circuit design, the virtual component comprising a virtual component body having at least one circuit function and a verification-supporting circuit detachably connected to the virtual component body. The verification-supporting circuit may include a verification-output terminal described by the hardware description language. The verification-output terminal is configured to output a signal indicating an operation state inside of the virtual component body, and is detachably connected to the virtual component body so as not to affect the operation of the virtual component body even when the connection of the verification-output terminal with the virtual component body is cut.
    • 一种用描述用于集成电路设计的虚拟部件的硬件描述语言编码的计算机可读介质,所述虚拟部件包括具有至少一个电路功能的虚拟部件主体和可拆卸地连接到虚拟部件主体的验证支持电路。 验证支持电路可以包括由硬件描述语言描述的验证输出终端。 验证输出端子被配置为输出指示虚拟组件主体内部的操作状态的信号,并且可拆卸地连接到虚拟组件主体,以便即使在验证连接时也不影响虚拟组件主体的操作 - 虚拟组件主体的输出端被切断。