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11. 发明授权

US06243306B1 Defect management engine for generating a unified address to access memory cells in a primary and a redundancy memory array 失效
标题翻译：缺陷管理引擎，用于生成统一的地址，以访问主和冗余存储器阵列中的存储单元
公开(公告)号：US06243306B1
公开(公告)日：2001-06-05
申请号：US09619257
申请日：2000-07-19
申请人： Toshiaki Kirihata
发明人： Toshiaki Kirihata
IPC分类号： G11C700
CPC分类号： G11C29/76 , G11C29/808
摘要： A method and apparatus for eliminating defects present in memory devices by way of a defect management engine (DME) is described. The DME integrates a plurality of defective address cells and redundancy address cells within an array. The defective address cells store addresses for accessing defective cells in a main memory. The redundancy address cells store addresses for accessing redundancy cells within a redundancy memory. The address data in the defective address cells is compared to the address input of the DME, thereby providing a redundancy match detection scheme. When no match occurs, the DME outputs the address input of the DME, which allows the main memory to be accessed when operating in a normal mode. When a match occurs, the DME outputs the address read from the redundancy address cells, which allows the redundancy memory to be accessed when operating in a redundancy mode.
摘要翻译：描述了通过缺陷管理引擎（DME）消除存储在设备中的缺陷的方法和装置。 DME在阵列内集成了多个缺陷地址单元和冗余地址单元。缺陷地址单元存储用于访问主存储器中的有缺陷单元的地址。冗余地址单元存储用于访问冗余存储器内的冗余单元的地址。将缺陷地址单元中的地址数据与DME的地址输入进行比较，从而提供冗余匹配检测方案。当不匹配时，DME输出DME的地址输入，允许在正常模式下工作时访问主存储器。当匹配发生时，DME输出从冗余地址单元读取的地址，这允许在冗余模式下操作时访问冗余存储器。

12. 发明授权

US6081479A Hierarchical prefetch for semiconductor memories 有权
标题翻译：半导体存储器的分层预取
公开(公告)号：US6081479A
公开(公告)日：2000-06-27
申请号：US333539
申请日：1999-06-15
申请人： Brian Ji , Toshiaki Kirihata , Gerhard Mueller , David Hanson
发明人： Brian Ji , Toshiaki Kirihata , Gerhard Mueller , David Hanson
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1039
摘要： A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.
摘要翻译：根据本发明的半导体存储器包括包括多个分层级的数据路径，每个级包括与其他级不同的位数据速率。至少两个预取电路设置在各级之间。至少两个预取电路包括用于接收数据位并存储数据位的至少两个锁存器，直到层级中的下一级能够接收数据位。所述至少两个预取电路耦合在级之间，使得级之间每级的总体数据速率基本相等。控制信号控制至少两个锁存器，使得预取电路保持级之间的总体数据速率。

13. 发明授权

US6052318A Repairable semiconductor memory circuit having parrel redundancy replacement wherein redundancy elements replace failed elements 有权
标题翻译：具有对等冗余替换的可修复半导体存储器电路，其中冗余元件代替故障元件
公开(公告)号：US6052318A
公开(公告)日：2000-04-18
申请号：US218561
申请日：1998-12-22
申请人： Toshiaki Kirihata , Gabriel Daniel
发明人： Toshiaki Kirihata , Gabriel Daniel
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C29/816 , G11C11/401
摘要： The present disclosure relates to semiconductor memories and more particularly, to an improved method and apparatus for replacing defective row/column lines. In accordance with the present invention, a high replacement flexibility redundancy and method is employed to increase chip yield and prevent sense amplifier signal contention. Redundancy elements are integrated in at least two of a plurality of memory arrays, which don't share the sense amplifiers. Thus, no additional sense amplifiers are required. A defective row/column line in a first array or block is replaced with a redundant row/column line from its own redundancy. A corresponding row/column line whether defective or not is replaced in a second array or block, which does not share sense amplifiers with the first block. The corresponding row/column is replaced to mimic the redundancy replacement of the first block thereby increasing flexibility and yield as well as preventing sensing signal contention.
摘要翻译：本公开涉及半导体存储器，更具体地，涉及用于替换有缺陷的行/列线的改进的方法和装置。根据本发明，采用高替换灵活性冗余和方法来提高芯片产量并防止感测放大器信号争用。冗余元件集成在不共享读出放大器的多个存储器阵列中的至少两个中。因此，不需要额外的感测放大器。第一个阵列或块中的有缺陷的行/列线被自己的冗余中的冗余行/列线代替。无论是否有故障，相应的行/列线被替换为不与第一块共享读出放大器的第二阵列或块。相应的行/列被替换以模拟第一块的冗余替换，从而增加灵活性和产量以及防止感测信号争用。

14. 发明授权

US5949732A Method of structuring a multi-bank DRAM into a hierarchical column select line architecture 失效
标题翻译：将多存储体DRAM构造为分层列选择行架构的方法
公开(公告)号：US5949732A
公开(公告)日：1999-09-07
申请号：US927160
申请日：1997-09-11
申请人： Toshiaki Kirihata
发明人： Toshiaki Kirihata
IPC分类号： G11C7/18 , G11C11/4091 , G11C8/00
CPC分类号： G11C11/4091 , G11C7/18
摘要： A method of structuring a multi-bank DRAM into a hierarchical column select line architecture is described. The DRAM is provided with a plurality of memory cells which are organized in at least two banks. Each of the banks includes memory cells which are arranged in rows and columns. The memory cells store data provided by at least one bit line and at least one data line. The DRAM includes: a first switch for selecting one of the two banks; and a second switch connected to the first switch for selecting one of the columns, wherein the first and second switches couple one of the bit lines to one of the data lines, enabling data to be written into or read out of memory cells common to the selected bank and to the selected column. The first switch is controlled by a plurality of bank CSLs (BCSLs), wherein the BCSLs are shared by some of the blocks within the same bank, but not by any of the blocks in other banks. The second switch is controlled by a plurality of global CSLs (GCSLs), the GCSLs being shared by all remaining banks within a unit. The BCSLs and GCSLs are controlled by the bank column decoder and global column decoder.
摘要翻译：描述了将多存储体DRAM构造成分层列选择线架构的方法。 DRAM具有被组织在至少两个组中的多个存储单元。每个存储体包括排列成行和列的存储单元。存储器单元存储由至少一个位线和至少一个数据线提供的数据。 DRAM包括：用于选择两个银行之一的第一开关; 以及第二开关，其连接到所述第一开关，用于选择所述列之一，其中所述第一和第二开关将所述位线中的一个耦合到所述数据线中的一个，使得能够将数据写入或读出与选定的银行和选定的列。第一开关由多个银行CSL（BCSL）控制，其中BCSL由同一银行内的一些块共享，但不由其他银行中的任何块共享。第二开关由多个全局CSL（GCSL）控制，GCSL由单元内的所有剩余的单元共享。 BCSL和GCSL由银行列解码器和全局列解码器控制。

15. 发明授权

US5877994A Space-efficient MDQ switch placement 失效
标题翻译：节省空间的MDQ开关放置
公开(公告)号：US5877994A
公开(公告)日：1999-03-02
申请号：US938073
申请日：1997-09-26
申请人： Gerhard Mueller , Toshiaki Kirihata
发明人： Gerhard Mueller , Toshiaki Kirihata
IPC分类号： G11C11/403 , G11C7/06 , G11C11/409 , G11C11/4091 , H01L21/8242 , H01L27/108 , G11C7/02 , G11C5/02 , G11C5/06 , G11C8/00
CPC分类号： G11C11/4091 , G11C7/065
摘要： A semiconductor memory having a plurality of memory cells arranged in rows and columns includes a bank of sense amplifiers disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier in the bank disposed in a sense amplifier region between a pair of complementary bit lines of an associated column. An MDQ switch being located in a sense amplifier region occupying a corresponding row-wise space to the at least one driver to provide space efficient placement thereof.
摘要翻译：具有排列成行和列的多个存储单元的半导体存储器包括布置在具有与所述行平行的长度的第一大致矩形区域中的读出放大器组，其中存储体中的每个读出放大器设置在读出放大器区域之间，一对相关列的互补位线。 MDQ开关位于感测放大器区域中，占据与至少一个驱动器相对应的行方向空间以提供空间高效的放置。

16. 发明授权

US5864496A High density semiconductor memory having diagonal bit lines and dual word lines 失效
标题翻译：具有对角位线和双字线的高密度半导体存储器
公开(公告)号：US5864496A
公开(公告)日：1999-01-26
申请号：US939455
申请日：1997-09-29
申请人： Gerhard Mueller , Toshiaki Kirihata , Heinz Hoenigschmid
发明人： Gerhard Mueller , Toshiaki Kirihata , Heinz Hoenigschmid
IPC分类号： H01L27/108 , G11C7/18 , G11C11/4097 , H01L21/8242 , G11C5/08
CPC分类号： H01L27/10891 , G11C11/4097 , G11C7/18 , H01L27/10861
摘要： The semiconductor memory includes a memory cell array (10) of memory cells arranged in rows and columns, and a plurality of diagonal bit lines (BLP.sub.1 -BLP.sub.N) arranged in a pattern that changes horizontal direction along the memory cell array to facilitate access to said memory cells. The bit lines are arranged non-orthogonal to a plurality of dual word lines (WL.sub.1 -WL.sub.M), where each dual word line includes a master word line (MWL.sub.i) at a first layer and a plurality of local word lines (LWL.sub.1 -LWL.sub.X) at a second layer. The local word lines are connected to the master word line of a common row via a plurality of spaced electrical connections (29), e.g., electrical contacts in a "stitched" architecture, and each local word line is connected to plural memory cells (MC). The electrical connections run in substantially the same pattern along the memory cell array as the bit lines.
摘要翻译：半导体存储器包括以行和列排列的存储器单元的存储单元阵列（10）和以沿存储单元阵列改变水平方向的图案布置的多个对角位线（BLP1-BLPN），以便于访问所述记忆细胞位线布置成与多条双字线（WL1-WLM）非正交，其中每个双字线包括第一层的主字线（MWLi）和多个本地字线（LWL1-LWLX）在第二层。本地字线经由多个间隔的电连接（29）连接到公共行的主字线，例如“缝合”结构中的电触点，并且每个本地字线连接到多个存储单元（MC ）。电连接沿着与位线的存储单元阵列基本上相同的图案运行。

17. 发明授权

US5822268A Hierarchical column select line architecture for multi-bank DRAMs 失效
标题翻译：多行DRAM的分层列选择线架构
公开(公告)号：US5822268A
公开(公告)日：1998-10-13
申请号：US927158
申请日：1997-09-11
申请人： Toshiaki Kirihata
发明人： Toshiaki Kirihata
IPC分类号： G11C7/10 , G11C8/12 , G11C11/408 , G11C11/4096 , G11C8/00
CPC分类号： G11C7/10 , G11C11/408 , G11C11/4096 , G11C7/1006 , G11C8/12
摘要： A multi-bank DRAM having a hierarchical column select line architecture is described. The DRAM is provided with a plurality of memory cells which are organized in at least two banks. Each of the banks includes memory cells which are arranged in rows and columns. The memory cells store data provided by at least one bit line and at least one data line. The DRAM includes: a first switch for selecting one of the two banks; and a second switch connected to the first switch for selecting one of the columns, wherein the first and second switches couple one of the bit lines to one of the data lines, enabling data to be written into or read out of memory cells common to the selected bank and to the selected column. The first switch is controlled by a plurality of bank CSLs (BCSLs), wherein the BCSLs are shared by some of the blocks within the same bank, but not by any of the blocks in other banks. The second switch is controlled by a plurality of global CSLs (GCSLs), the GCSLs being shared by all remaining banks within a unit. The BCSLs and GCSLs are controlled by the bank column decoder and by the global column decoder.
摘要翻译：描述具有分层列选择线架构的多存储体DRAM。 DRAM具有被组织在至少两个组中的多个存储单元。每个存储体包括排列成行和列的存储单元。存储器单元存储由至少一个位线和至少一个数据线提供的数据。 DRAM包括：用于选择两个银行之一的第一开关; 以及第二开关，其连接到所述第一开关，用于选择所述列之一，其中所述第一和第二开关将所述位线中的一个耦合到所述数据线中的一个，使得能够将数据写入或读出与选定的银行和选定的列。第一开关由多个银行CSL（BCSL）控制，其中BCSL由同一银行内的一些块共享，但不由其他银行中的任何块共享。第二开关由多个全局CSL（GCSL）控制，GCSL由单元内的所有剩余的单元共享。 BCSL和GCSL由银行列解码器和全局列解码器控制。

18. 发明授权

US5691946A Row redundancy block architecture 失效
标题翻译：行冗余块架构
公开(公告)号：US5691946A
公开(公告)日：1997-11-25
申请号：US758783
申请日：1996-12-03
申请人： John DeBrosse , Toshiaki Kirihata , Hing Wong
发明人： John DeBrosse , Toshiaki Kirihata , Hing Wong
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L27/108 , G11C5/06
CPC分类号： G11C29/80 , G11C29/808 , G11C29/84
摘要： Row redundancy control circuits which effectively reduce design space are arranged parallel to word direction and are arranged at the bottom of the redundancy block. This architecture change makes it possible to effectively lay out the redundancy control block by introducing (1) split-global-bus shared with local row redundancy wires, (2) half-length-one-way row redundancy-wordline-enable-signal wires which allows space saving, and (3) distributed wordline enable decoders designed to take advantage of the saved space. An illegal normal/redundancy access problem caused by the address versus timing skew has also been solved. The timing necessary for this detection is given locally by using its adjacent redundancy match detection. This allows the circuit to operate completely as an address driven circuit, resulting in fast and reliable redundancy match detection. In addition, a sample wordline enable signal (SWLE) is generated by using row redundancy match detection. One two-input OR gate allows the time at which SWLE sets sample wordline (SWL) to be the same as the time at which wordline enable (WLE) signal sets wordline (WL). The time at which SWLE sets SWL remains consistent regardless of mode, eliminating the existing reliability concern. This two-input OR gate combined with row redundancy match detection works as an ideal sample wordline enable generator.
摘要翻译：有效减少设计空间的行冗余控制电路与字方向平行排列，并配置在冗余块的底部。通过引入（1）与本地行冗余线共享的分裂全局总线，（2）半长度单向行冗余字线使能信号线，可以有效地布置冗余控制块这允许节省空间，以及（3）分布式字线使能解码器被设计为利用节省的空间。由地址与时序偏差引起的非法正常/冗余访问问题也已解决。通过使用其相邻的冗余匹配检测在本地给出该检测所需的定时。这允许电路作为地址驱动电路完全操作，导致快速可靠的冗余匹配检测。此外，通过使用行冗余匹配检测来生成采样字线使能信号（SWLE）。一个双输入或门允许SWLE设置采样字线（SWL）的时间与字线使能（WLE）信号设置字线（WL）的时间相同。无论模式如何，SWLE设置SWL的时间保持一致，从而消除了现有的可靠性问题。该双输入OR门与行冗余匹配检测相结合，可作为理想的采样字线使能发生器。

19. 发明授权

US5544113A Random access memory having a flexible array redundancy scheme 失效
标题翻译：具有灵活阵列冗余方案的随机存取存储器
公开(公告)号：US5544113A
公开(公告)日：1996-08-06
申请号：US346965
申请日：1994-11-30
申请人： Toshiaki Kirihata , Yohji Watanabe
发明人： Toshiaki Kirihata , Yohji Watanabe
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/808
摘要： A wide Input/Output (I/O) Random Access Memory (RAM) with more efficient redundancy. The RAM array may be divided into individual units. Each unit is further divided into subarray blocks (blocks of subarrays). Each subarray or segment is organized by one and includes one spare column and may include spare word lines. When a block is accessed, only half of the segments are accessed. Whenever a segment is accessed, the segment's spare column is not. The spare columns from the unaccessed half block are available for repairing defective columns in the accessed half block. Data from columns in the accessed half and spare columns in the unaccessed half are transferred to Local Data Lines (LDLs) and from LDLs to Master Data Lines (MDLs). Valid data from accessed column lines and from selected spare lines are provided on the MDLS to second sense amplifiers. Defective columns are electrically replaced with spares after the second stage amplifiers. Thus, all of the spare columns in each half of each subarray block are available to replace an equal number of failed columns at any location in any segment in the other half block.
摘要翻译：具有更高效冗余的宽输入/输出（I / O）随机存取存储器（RAM）。 RAM阵列可以被分成单独的单元。每个单元进一步分为子阵列（子阵列）。每个子阵列或段由一个组成，并且包括一个备用列，并且可以包括备用字线。访问块时，仅访问一半的段。无论何时访问段，段的备用列都不存在。来自未加工的半块的备用列可用于修复访问的半块中的有缺陷的列。未访问的一半中的列中的数据和未加工的一半中的备用列的数据将传输到本地数据线（LDL），并从LDL传输到主数据线（MDL）。在MDLS上向第二读出放大器提供来自所访问列线和选定备用线路的有效数据。在第二级放大器之后，有缺陷的列被替换为备件。因此，每个子阵列块的每一半中的所有备用列可用于在另一半块中的任何段中的任何位置处替换相等数量的故障列。

20. 发明授权

US5483179A Data output drivers with pull-up devices 失效
标题翻译：具有上拉设备的数据输出驱动器
公开(公告)号：US5483179A
公开(公告)日：1996-01-09
申请号：US230265
申请日：1994-04-20
申请人： Sang H. Dhong , Toshiaki Kirihata , Matthew R. Wordeman
发明人： Sang H. Dhong , Toshiaki Kirihata , Matthew R. Wordeman
IPC分类号： H03K17/687 , G05F3/24 , H03K19/0175 , H01L25/00
CPC分类号： G05F3/24
摘要： A device for controlling the voltage across an NMOS pull-up transistor including a source node which may be exposed to a variable voltage. The device further includes a gate node which may be exposed to a variable voltage. A control portion regulates the voltage applied to the gate node, wherein a differential in voltage between the source node and the gate node is limited to a desired level.
摘要翻译：用于控制跨越NMOS上拉晶体管的电压的装置，其包括可能暴露于可变电压的源节点。该器件还包括可以暴露于可变电压的栅极节点。控制部分调节施加到栅极节点的电压，其中源节点和栅极节点之间的电压差被限制到期望的电平。

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