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11. 发明授权

US6150237A Method of fabricating STI 失效
标题翻译：制作STI的方法
公开(公告)号：US6150237A
公开(公告)日：2000-11-21
申请号：US420049
申请日：1999-10-18
申请人： Tong-Hsin Lee
发明人： Tong-Hsin Lee
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232
摘要： A fabrication method for shallow trench isolation (STI) is briefly described as follows. A substrate is provided with a patterned mask layer and pad oxide layer formed thereon, so that a first opening, which exposes a part of the substrate, is formed. A shallow trench is then formed in the substrate, followed by filling the shallow trench with a first insulating layer, wherein the surface of the first insulating layer is lower than the surface of the substrate, and a part of the substrate forming the sidewall of the shallow trench is exposed. A part of the mask layer and pad oxide layer is removed to enlarge the first opening, so that a second opening, which exposes a part of the substrate, is formed. A doped region is formed on the exposed part of the substrate, while the second opening and the shallow trench are filled with a second insulating layer. Finally, the mask layer and the pad oxide layer are removed in sequence to complete the manufacture of the STI.
摘要翻译：浅沟槽隔离（STI）的制造方法简要描述如下。衬底上设置有图案化的掩模层和衬垫氧化物层，从而形成露出一部分衬底的第一开口。然后在衬底中形成浅沟槽，然后用第一绝缘层填充浅沟槽，其中第一绝缘层的表面低于衬底的表面，并且形成衬底的侧壁的一部分浅沟被暴露。除去掩模层和焊盘氧化物层的一部分以扩大第一开口，从而形成露出一部分基板的第二开口。掺杂区域形成在衬底的暴露部分上，而第二开口和浅沟槽填充有第二绝缘层。最后，依次去除掩模层和焊盘氧化物层，以完成STI的制造。

12. 发明授权

US6043154A Method for manufacturing charge storage electrode 失效
标题翻译：电荷存储电极的制造方法
公开(公告)号：US6043154A
公开(公告)日：2000-03-28
申请号：US57599
申请日：1998-04-08
申请人： Tong-Hsin Lee
发明人： Tong-Hsin Lee
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242
CPC分类号： H01L28/82 , H01L21/76895
摘要： A method for manufacturing a charge storage electrode that utilizes the tendency for implanted phosphorus ions in a hemispherical grain (HSG) polysilicon layer to gather near the grooves so that the rate of oxidation there increases. Utilizing this property, a solution including an oxidizing agent and an etching agent mixed in a specified ratio is employed to etch the hemispherical grained polysilicon layer so that the grooves in the hemispherical polysilicon layer is deepened. Therefore, the surface area of the charge storage electrode is increased, and hence capacitance of the charge storage structure becomes greater. Moreover, the method used in this invention is compatible with the conventional processes and can be produced in batches. Therefore, production cost is low.
摘要翻译：一种利用在半球状晶粒（HSG）多晶硅层中注入磷离子的趋势的电荷存储电极的制造方法，在沟槽附近聚集，使得氧化速率增加。利用该性质，采用包含以规定比例混合的氧化剂和蚀刻剂的溶液来蚀刻半球状粒状多晶硅层，使得半球状多晶硅层中的沟槽加深。因此，电荷存储电极的表面积增加，因此电荷存储结构的电容变大。此外，本发明中使用的方法与常规方法兼容，可以批量生产。因此，生产成本低。

13. 发明授权

US06534354B1 Method of manufacturing MOS transistor with fluorine implantation at a low energy 有权
标题翻译：以低能量制造氟注入的MOS晶体管的方法
公开(公告)号：US06534354B1
公开(公告)日：2003-03-18
申请号：US10004635
申请日：2001-12-04
申请人： Tong-Hsin Lee , Terry Chung-Yi Chen
发明人： Tong-Hsin Lee , Terry Chung-Yi Chen
IPC分类号： H01L218238
CPC分类号： H01L29/665 , H01L21/265 , H01L27/11 , Y10S438/919
摘要： A method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D) implantation is conducted to form a source/drain region in the substrate on each side of the gate electrode. A self-aligned silicide (Salicide) process is carried out to form a self-aligned silicide layer over the exposed gate electrode and source/drain region. A silicon nitride layer serving as an etching stop is formed over the substrate. A fluoride blanket implantation of the silicon nitride etching stop layer is carried out using an implantation dosage of about 5×1013˜5×1014 cm−2 and at an implantation energy level between 2 KeV˜5 KeV. The fluorides implanted into the silicon nitride layer capture hydrogen within the silicon nitride layer, thereby reducing free hydrogen concentration and increasing threshold voltage stability of the MOS transistor.
摘要翻译：一种制造MOS晶体管的方法。提供了具有栅极氧化物层，栅电极和附着到栅电极的侧壁的间隔物的衬底。进行源极/漏极（S / D）注入以在栅电极的每一侧上的衬底中形成源极/漏极区域。进行自对准硅化物（硅化物）工艺以在暴露的栅极电极和源极/漏极区域上形成自对准的硅化物层。在衬底上形成用作蚀刻停止层的氮化硅层。氮化硅蚀刻停止层的氟化物覆盖层注入使用约5×10 13〜5×10 14 cm -2的注入剂量和2KeV〜5KeV之间的注入能级进行。注入氮化硅层的氟化物捕获氮化硅层内的氢，从而降低自由氢浓度并增加MOS晶体管的阈值电压稳定性。

14. 发明授权

US06251737B1 Method of increasing gate surface area for depositing silicide material 失效
标题翻译：增加沉积硅化物材料的栅极表面积的方法
公开(公告)号：US06251737B1
公开(公告)日：2001-06-26
申请号：US09434047
申请日：1999-11-04
申请人： Tong-Hsin Lee
发明人： Tong-Hsin Lee
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/6659
摘要： A method for increasing gate surface area for depositing silicide material. A silicon substrate having device isolation structures therein is provided. A stack of sacrificial layers comprising a first sacrificial layer at the bottom, a second sacrificial layer in the middle and a third sacrificial layer on top is formed over the silicon substrate. A gate opening that exposes a portion of the substrate is formed in the stack of sacrificial layers. A portion of the second sacrificial layer exposed by the gate opening is next removed to form a side opening on each side of the gate opening. The gate opening together with the horizontal side opening form a cross-shaped hollow space. A gate oxide layer is formed at the bottom of the gate opening. Polysilicon material is deposited to fill the gate opening and the side openings, thereby forming a cross-shaped gate polysilicon layer. The third, the second and the first sacrificial layers are removed. A metal silicide layer is formed over the gate polysilicon layer.
摘要翻译：一种用于增加用于沉积硅化物材料的栅极表面积的方法。提供了其中具有器件隔离结构的硅衬底。在硅衬底上形成堆叠的牺牲层，其包括底部的第一牺牲层，中间的第二牺牲层和顶部的第三牺牲层。在牺牲层的堆叠中形成露出基板的一部分的栅极开口。接下来去除由栅极开口暴露的第二牺牲层的一部分，以在栅极开口的每一侧上形成侧开口。门开口与水平侧开口一起形成十字形的中空空间。栅极氧化层形成在栅极开口的底部。沉积多晶硅材料以填充栅极开口和侧开口，从而形成十字形栅极多晶硅层。第三，第二和第一牺牲层被去除。在栅极多晶硅层上形成金属硅化物层。

15. 发明授权

US06228756B1 Method of manufacturing inter-metal dielectric layer 失效
标题翻译：制造金属间电介质层的方法
公开(公告)号：US06228756B1
公开(公告)日：2001-05-08
申请号：US09371472
申请日：1999-08-10
申请人： Tong-Hsin Lee
发明人： Tong-Hsin Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76801 , H01L21/316 , H01L21/7682 , H01L21/76832 , H01L21/76834
摘要： A method of manufacturing an inter-metal dielectric layer. A substrate having a plurality of wires formed thereon is provided. A portion of the substrate is exposed to form an opening between the wires. The opening is filled with a flowable dielectric material, wherein a surface level of the flowable dielectric material is lower than that of the wires. A plurality of spacers is formed on the sidewall of the wires exposed by the flowable dielectric material. The flowable dielectric material is removed. An anisotropic deposition process with a poor-lateral-filling ability is performed to form a dielectric layer with a void under the spacer over the substrate.
摘要翻译：一种制造金属间电介质层的方法。提供了在其上形成有多根线的基板。衬底的一部分被暴露以形成电线之间的开口。开口填充有可流动介电材料，其中可流动介电材料的表面水平低于导线的表面水平。在由可流动介电材料暴露的电线的侧壁上形成多个间隔物。去除可流动介电材料。执行具有差的侧向填充能力的各向异性沉积工艺以形成在衬底上的间隔物下方具有空隙的电介质层。

16. 发明授权

US6133091A Method of fabricating a lower electrode of capacitor 失效
标题翻译：制造电容器下电极的方法
公开(公告)号：US6133091A
公开(公告)日：2000-10-17
申请号：US434688
申请日：1999-11-05
申请人： Tong-Hsin Lee , Hsi-Mao Hsiao , Wen-Shan Wei , Chun-Lung Chen
发明人： Tong-Hsin Lee , Hsi-Mao Hsiao , Wen-Shan Wei , Chun-Lung Chen
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/20
CPC分类号： H01L28/87 , H01L27/10852
摘要： A method of fabricating a lower electrode of a capacitor. A sacrificial multilayer is formed on a semiconductor layer. The sacrificial multi-layer is a stack of alternating first and second sacrificial layers. A patterned first mask layer having a first opening above a conductive plug in the semiconductor substrate is formed on the sacrificial multi-layer. A planar spacer is formed on the sidewall of the first opening. A second mask layer is formed to fill the first opening. The planar spacer and the sacrificial multi-layer thereunder are anisotropically etched until the semiconductor substrate is exposed to form a second opening while using the first mask layer and second mask layer as a mask. The first sacrificial layers exposed by the second opening are isotropically etched to form a plurality of recesses. The second opening and the recesses are filled with a conductive material layer. Finally, the first mask layer, second mask layer, and sacrificial multi-layer are removed.
摘要翻译：一种制造电容器的下电极的方法。在半导体层上形成牺牲层。牺牲多层是交替的第一和第二牺牲层的堆叠。在牺牲多层上形成具有在半导体衬底中的导电插塞上方的第一开口的图案化的第一掩模层。平面间隔件形成在第一开口的侧壁上。形成第二掩模层以填充第一开口。在使用第一掩模层和第二掩模层作为掩模的同时，平面间隔物和其下的牺牲多层被各向异性蚀刻，直到半导体衬底暴露以形成第二开口。由第二开口暴露的第一牺牲层被各向同性蚀刻以形成多个凹部。第二开口和凹部填充有导电材料层。最后，去除第一掩模层，第二掩模层和牺牲多层。

17. 发明授权

US6127228A Method of forming buried bit line 有权
标题翻译：形成埋地线的方法
公开(公告)号：US6127228A
公开(公告)日：2000-10-03
申请号：US435399
申请日：1999-11-06
申请人： Tong-Hsin Lee
发明人： Tong-Hsin Lee
IPC分类号： H01L21/60 , H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/12 , H01L21/336
CPC分类号： H01L27/10885 , H01L21/76897 , H01L21/84 , H01L27/1203 , H01L27/10808 , H01L27/10888
摘要： A method of forming buried bit lines. A silicon-on-insulator (SOI) substrate includes a silicon base layer, a first insulation layer and an epitaxial silicon layer. A shallow trench isolation (STI) layer that contacts the first insulation layer is formed in the epitaxial silicon layer. A trench that penetrates the STI layer and runs deep into the first insulation layer is formed. A buried bit line is formed inside the trench such that the top surface of the buried bit line is located between the upper and the lower surface of the STI layer. A second insulation layer is next formed over the buried bit line such that the top surface of the second insulation layer is at the same level as the top surface of the epitaxial silicon layer. A plurality of word lines and a plurality of source/drain regions are formed over the substrate and in the epitaxial silicon layer. A third insulation layer is formed over the substrate, filling the space between the word lines such that the top surface of the third insulation layer is at the same level as the top surface of the word lines. A self-aligned contact process is carried out to form a bit line contact opening between the word lines. The bit line contact opening exposes the buried bit line and a portion of the source/drain region. Finally, bit line contact is formed in the bit line contact opening.
摘要翻译：一种形成掩埋位线的方法。绝缘体上硅（SOI）衬底包括硅基底层，第一绝缘层和外延硅层。在外延硅层中形成接触第一绝缘层的浅沟槽隔离层（STI）层。形成穿透STI层并深入第一绝缘层的沟槽。埋入位线形成在沟槽内，使得掩埋位线的顶表面位于STI层的上表面和下表面之间。接下来在掩埋位线上形成第二绝缘层，使得第二绝缘层的顶表面与外延硅层的顶表面处于相同的水平。在衬底和外延硅层中形成多个字线和多个源/漏区。第三绝缘层形成在衬底上，填充字线之间的空间，使得第三绝缘层的顶表面与字线的顶表面处于相同的高度。进行自对准的接触处理以在字线之间形成位线接触开口。位线接触开口暴露了掩埋位线和源极/漏极区域的一部分。最后，在位线接触开口中形成位线接触。

18. 发明授权

US6093600A Method of fabricating a dynamic random-access memory device 失效
标题翻译：制造动态随机存取存储器件的方法
公开(公告)号：US6093600A
公开(公告)日：2000-07-25
申请号：US430706
申请日：1999-10-29
申请人： Terry Chung-Yi Chen , Tong-Hsin Lee
发明人： Terry Chung-Yi Chen , Tong-Hsin Lee
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10835 , H01L27/10861 , H01L21/76895 , H01L28/60
摘要： A method of fabricating a dynamic random-access memory (DRAM) device integrates a shallow trench isolation (STI) process and a storage node process into the fabrication of the DRAM device. With a bit line over capacitor (BOC) structure, the capacitor is laid out in parts of the shallow trench isolation structure to increase the surface area of the storage node by using the trench. During the fabrication of the capacitor, a stacked plug used to connect the bit line is formed. The stacked plug used as the interconnection in the circuit region is also formed. An insulating layer is formed to cover the capacitor, and an opening is formed therein to expose the stacked plug. A bit line and an interconnection are formed on the insulating layer to connect with a conducting layer which is located in the stacked plug and contacted with the source/drain regions.
摘要翻译：制造动态随机存取存储器（DRAM）器件的方法将浅沟槽隔离（STI）处理和存储节点处理集成到DRAM器件的制造中。通过在电容器（BOC）结构上的位线，电容器布置在浅沟槽隔离结构的部分中，以通过使用沟槽来增加存储节点的表面积。在制造电容器期间，形成用于连接位线的堆叠式插头。还形成了用作电路区域中的互连的堆叠插头。形成绝缘层以覆盖电容器，并且在其中形成开口以露出堆叠的插塞。在绝缘层上形成位线和互连，以与位于堆叠式插头中并与源极/漏极区域接触的导电层连接。

19. 发明授权

US5932333A Method for manufacturing charge storage electrode 失效
公开(公告)号：US5932333A
公开(公告)日：1999-08-03
申请号：US57925
申请日：1998-04-08
申请人： Tong-Hsin Lee
发明人： Tong-Hsin Lee
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/84
摘要： A method for manufacturing a charge storage electrode that utilizes the tendency for implanted phosphorus ions in a hemispherical grain (HSG) polysilicon layer to gather near the grooves so that the rate of oxidation there increases. Utilizing this property, a solution including an oxidizing agent and an etching agent mixed in a specified ratio is employed to etch the hemispherical grained polysilicon layer so that the grooves in the hemispherical polysilicon layer is deepened. Therefore, the surface area of the charge storage electrode is increased, and hence capacitance of the charge storage structure becomes greater. Moreover, the method used in this invention is compatible with the conventional processes and can be produced in batches. Therefore, production cost is low.

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