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11. 发明授权

US6118718A Semiconductor memory device in which a BIT line pair having a high load is electrically separated from a sense amplifier 有权
标题翻译：具有高负载的BIT线对与读出放大器电隔离的半导体存储器件
公开(公告)号：US6118718A
公开(公告)日：2000-09-12
申请号：US440321
申请日：1999-11-12
申请人： Yoshikazu Yabe
发明人： Yoshikazu Yabe
IPC分类号： G11C11/409 , G11C7/02 , G11C7/06 , G11C8/00 , G11C8/06
CPC分类号： G11C7/06 , G11C8/00 , G11C8/06
摘要： When a minute electric potential difference on a bit line pair is transmitted to sense amplifier, a bit line pair having a high load is electrically separated from the sense amplifier, thereby performing amplification. Therefore, reading speed can be increased. Furthermore, a plurality of sense amplifier are provided corresponding to each bit line pair. While any of the sense amplifier amplifies the read data, data held in another sense amplifier are written to the memory cell through the corresponding bit line pair. Consequently, in the case where the writing and reading operations are carried out alternately, the delay of a reading operation start period can be reduced during the writing operation. Consequently, it is possible to implement a memory device capable of increasing reading speed and reducing the delay of the reading operation start period by the writing operation even if writing frequency is almost equal to reading frequency.
摘要翻译：当位线对上的微小电位差被发送到读出放大器时，具有高负载的位线对与读出放大器电分离，从而进行放大。因此，可以提高读取速度。此外，对应于每个位线对提供多个读出放大器。而任何一个读出放大器放大读取的数据，保存在另一个读出放大器中的数据通过相应的位线对写入存储单元。因此，在写入和读取操作交替执行的情况下，可以在写入操作期间减少读取操作开始时段的延迟。因此，即使写入频率几乎等于读取频率，也可以实现能够通过写入操作增加读取速度并减少读取操作开始时段的延迟的存储器件。

12. 发明授权

US07523292B2 Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix 有权
标题翻译：具有状态控制单元的阵列式处理器，其控制以矩阵形式布置的多个处理器元件
公开(公告)号：US07523292B2
公开(公告)日：2009-04-21
申请号：US10682830
申请日：2003-10-10
申请人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
发明人： Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/8007
摘要： A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are switch-controlled, are arranged in matrix form, and the instruction codes of this multiplicity of processor elements are successively switched by a state control unit. The state control units are composed of a plurality of units that intercommunicate to realize linked operation, and the multiplicity of processor elements is divided into a number of element areas that corresponds to the number of state control units. The plurality of state control units are arranged for each of the plurality of element areas and are connected to the processor elements, whereby the plurality of state control units can individually control a plurality of small-scale state transitions, or the plurality of state control units can cooperate to control a single large-scale state transition.
摘要翻译：多个处理器元件分别按照已经被设置为数据并且相互连接关系被切换控制的指令代码单独执行数据处理，以矩阵形式排列，并且该多个处理器元件的指令代码被状态控制单元依次切换。状态控制单元由多个单元组成，这些单元相互通信以实现链接操作，并且多个处理器元件被分成与状态控制单元数量相对应的多个元件区域。多个状态控制单元被布置用于多个元件区域中的每一个，并且连接到处理器元件，由此多个状态控制单元可以单独地控制多个小规模状态转换，或者多个状态控制单元可以合作控制单一的大规模国家转型。

13. 发明申请

US20080201526A1 Array-type processor having delay adjusting circuit 有权
标题翻译：具有延迟调整电路的阵列式处理器
公开(公告)号：US20080201526A1
公开(公告)日：2008-08-21
申请号：US12071221
申请日：2008-02-19
申请人： Yoshikazu Yabe
发明人： Yoshikazu Yabe
IPC分类号： G06F12/00
CPC分类号： G06F1/04 , G06F15/7867
摘要： Disclosed is an array-type processor including a data path unit in which a plurality of processor elements are arranged in an array; a state-transition management unit that stores information for controlling changeover of data paths; and a delay adjusting circuit that adjusts delay of the input clock signal based upon information output from the state-transition management unit, and provides the delay-adjusted clock signal to the data path unit. The delay adjusting circuit has a delay control information memory and a programmable delay. The delay control information memory stores a plurality of items of delay control information, delay control information is read out using a configuration number supplied from the state-transition management unit as an address, and the delay control information is applied to the programmable array. The programmable delay delays the input clock signal by a delay time specified by the delay control information and provides the delayed clock signal to the data path unit.
摘要翻译：公开了一种阵列型处理器，包括数据路径单元，其中多个处理器元件排列成阵列; 状态转移管理单元，其存储用于控制数据路径的切换的信息; 以及延迟调整电路，其根据从状态转移管理单元输出的信息来调整输入时钟信号的延迟，并将延迟调整的时钟信号提供给数据路径单元。延迟调整电路具有延迟控制信息存储器和可编程延迟。延迟控制信息存储器存储多个延迟控制信息项，使用从状态转换管理单元提供的配置号作为地址读出延迟控制信息，并将延迟控制信息应用于可编程阵列。可编程延迟将输入时钟信号延迟延迟控制信息指定的延迟时间，并将延迟的时钟信号提供给数据路径单元。

14. 发明授权

US07752420B2 Configuration layout number controlled adjustable delaying of connection path changes among processors in array to reduce transition glitches 失效
标题翻译：配置布局编号控制阵列中处理器之间连接路径变化的可调节延迟，以减少转换毛刺
公开(公告)号：US07752420B2
公开(公告)日：2010-07-06
申请号：US12030619
申请日：2008-02-13
申请人： Yoshitaka Izawa , Yoshikazu Yabe
发明人： Yoshitaka Izawa , Yoshikazu Yabe
IPC分类号： G06F15/80 , G06F1/04
CPC分类号： G06F15/7867 , H03K17/002 , Y02D10/12 , Y02D10/13
摘要： Occurrence and propagation of glitches caused by changing the path layout are suppressed, thereby reducing the power consumption. An array-type processor comprises a plurality of processor elements and can change the path layout relating to data transmission/reception between the processor elements depending on clock cycle. Each processor element comprises a layout information memory 11 that stores a layout information indicating signal relating to the layout of the paths, a delay adjusting circuit 12 that adjusts the timing of a layout information indicating signal Pin outputted from the layout information memory 11 at every clock cycle, and a wiring connection circuit 13 that changes a path to at least one of the other processor elements (PE) or function unit(s) (a register file unit 14 and an arithmetic logic unit 15) based on a layout information indicating signal Pout whose timing has been adjusted.
摘要翻译：通过改变路径布局导致的毛刺的发生和传播被抑制，从而降低功耗。阵列式处理器包括多个处理器元件，并且可以根据时钟周期改变与处理器元件之间的数据发送/接收有关的路径布局。每个处理器元件包括布局信息存储器11，其存储指示与路径布局相关的信号的布局信息;延迟调整电路12，其调整布局信息存储器11在每个时钟输出的布局信息指示信号Pin的定时循环，以及基于布局信息指示信号改变到其他处理器元件（PE）或功能单元（寄存器文件单元14和算术逻辑单元15）中的至少一个的路径的布线连接电路13 Pout的时间调整了。

15. 发明授权

US06556484B2 Plural line buffer type memory LSI 失效
公开(公告)号：US06556484B2
公开(公告)日：2003-04-29
申请号：US09746809
申请日：2000-12-20
申请人： Yoshikazu Yabe , Masato Motomura
发明人： Yoshikazu Yabe , Masato Motomura
IPC分类号： G11C700
CPC分类号： G11C7/1039
摘要： In a plural line buffer type memory LSI, a line selection register 16 (holding an address for designating a line buffer) is added. The value of the line selection register 16 is previously updated by a memory access instruction having a room in an address. Thus, it is possible to maintain compatibility with input/output terminals of a general purpose memory LSI, or to prevent the increase in the number of input/output terminals, and also to prevent the increase of the memory access delay attributable to the restriction in connection with the issue of the commands. Accordingly, it is possible to maintain the compatibility with the general purpose memory LSI having no line buffer, or alternatively to prevent the increase of the memory access delay attributable to a restriction in an interval for issuing the commands.

16. 发明授权

US06490669B1 Memory LSI with compressed data inputting and outputting function 失效
标题翻译：具有压缩数据输入和输出功能的存储器LSI
公开(公告)号：US06490669B1
公开(公告)日：2002-12-03
申请号：US09374992
申请日：1999-08-16
申请人： Yoshikazu Yabe
发明人： Yoshikazu Yabe
IPC分类号： G06F1200
CPC分类号： G11C7/1006 , G11C2207/102
摘要： A memory LSI with compressed data inputting and outputting function provides reduction of data transfer amount and whereby to expand effective passband width with restricting transfer loss upon transfer of variable length compressed data. Data size detection circuit detects a size of a compressed data input from an external device on the basis of a compression information added to the compressed data and indicative of a size of data after compression. A data input and output circuit and an instruction decoder are operated for a period necessary for writing operation to write in the compressed data in a memory cell array. The data size detection circuit detects size of the compressed data held in the memory cell array on the basis of the compression information upon reading out to operate the data input and output circuit and the memory cell array for a period necessary for reading operating to read out compressed data to the external device.
摘要翻译：具有压缩数据输入和输出功能的存储器LSI提供数据传输量的减少，从而通过在传输可变长度压缩数据时限制传输损耗来扩展有效通带宽度。数据大小检测电路根据添加到压缩数据的压缩信息并且表示压缩后的数据的大小来检测从外部设备输入的压缩数据的大小。数据输入和输出电路和指令解码器在写操作所需的时间内被操作以写入存储单元阵列中的压缩数据。数据大小检测电路根据读出时的压缩信息来检测保存在存储单元阵列中的压缩数据的大小，以在数据输入和输出电路和存储单元阵列中操作读出操作所需的时间压缩数据到外部设备。

17. 发明授权

US06414880B1 Multiple line buffer type memory LSI 失效
公开(公告)号：US06414880B1
公开(公告)日：2002-07-02
申请号：US09933820
申请日：2001-08-22
申请人： Yoshikazu Yabe , Masato Motomura
发明人： Yoshikazu Yabe , Masato Motomura
IPC分类号： G11C700
CPC分类号： G11C7/1087 , G11C7/1051 , G11C7/1078
摘要： In a multiple line buffer type memory LSI, when line buffers retaining data read out from a memory section does not exist in a multiple line buffer section, data retained in any of the line buffers are copied and held temporarily in standby in the write-back buffers. The data read out from the memory section are retained in the line buffers. The data temporarily held in standby in the write-back buffers are written back into the memory section.

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