专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08581653B1 Techniques for providing clock signals in clock networks 有权
标题翻译：在时钟网络中提供时钟信号的技术
公开(公告)号：US08581653B1
公开(公告)日：2013-11-12
申请号：US13328784
申请日：2011-12-16
申请人： Victor Maruri , Arch Zaliznyak , Ramanand Venkata , Henry Y. Lui
发明人： Victor Maruri , Arch Zaliznyak , Ramanand Venkata , Henry Y. Lui
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10
摘要： An integrated circuit includes a local clock network that is operable to provide a first clock signal and an interface circuit that is coupled to receive the first clock signal from the local clock network. The interface circuit is operable to generate a second clock signal based on the first clock signal. A clock line is coupled to the interface circuit. The clock line has a fixed length. The second clock signal is provided to a multiplexer circuit through the clock line. The multiplexer circuit provides a third clock signal based on the second clock signal. Another clock network is coupled to receive the third clock signal from the multiplexer circuit.
摘要翻译：集成电路包括可操作以提供第一时钟信号的本地时钟网络和耦合以从本地时钟网络接收第一时钟信号的接口电路。接口电路可操作以基于第一时钟信号产生第二时钟信号。时钟线耦合到接口电路。时钟线具有固定长度。第二时钟信号通过时钟线提供给多路复用器电路。多路复用器电路基于第二时钟信号提供第三时钟信号。另一个时钟网络被耦合以从多路复用器电路接收第三时钟信号。

12. 发明授权

US08994425B2 Techniques for aligning and reducing skew in serial data signals 有权
标题翻译：用于对齐和减少串行数据信号偏移的技术
公开(公告)号：US08994425B2
公开(公告)日：2015-03-31
申请号：US13566882
申请日：2012-08-03
申请人： Ramanand Venkata , Henry Lui , Arch Zaliznyak
发明人： Ramanand Venkata , Henry Lui , Arch Zaliznyak
IPC分类号： H03L7/00 , H03K5/1534
CPC分类号： H03K5/1534
摘要： A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.
摘要翻译：一个电路包括第一和第二对准器电路和一个去歪斜电路。第一对准器电路可操作以将第一输入串行数据信号与控制信号对准以产生第一对准的串行数据信号。第二对准器电路可操作以将第二输入串行数据信号与控制信号对准以产生第二对准的串行数据信号。去偏置电路可操作以减少第一和第二对准的串行数据信号之间的偏差，以产生第一和第二输出串行数据信号。

13. 发明申请

US20070011370A1 Multiple data rates in programmable logic device serial interface 有权
标题翻译：可编程逻辑器件串行接口中的多个数据速率
公开(公告)号：US20070011370A1
公开(公告)日：2007-01-11
申请号：US11177007
申请日：2005-07-08
申请人： Ramanand Venkata , Rakesh Patel , Chong Lee
发明人： Ramanand Venkata , Rakesh Patel , Chong Lee
IPC分类号： G06F13/38
CPC分类号： H03K19/17744
摘要： A serial interface for a programmable logic device supports a wide range of data rates by providing a first number of channels supporting a first range of data rates and a second number of channels supporting a second range of data rates. The first range of data rates is preferably lower than the second range of data rates and preferably the first number of channels is higher than the second number of channels which preferably is 1. For backward compatibility with existing devices, the first number of channels in each interface preferably is four. Each channel preferably includes a physical medium attachment module and a physical coding sublayer module. Each of the higher-speed channels in the second number of channels preferably also includes a clock management unit, while the lower-speed channels in the first number of channels preferably share one or more clock management units.
摘要翻译：用于可编程逻辑器件的串行接口通过提供支持第一范围的数据速率的第一数量的通道和支持第二数据速率范围的第二数量的通道来支持宽范围的数据速率。数据速率的第一范围优选地低于数据速率的第二范围，并且优选地，第一数量的信道高于优选为1的信道的第二数量。为了与现有设备的向后兼容，每个信道中的第一数量的信道界面最好是四。每个通道优选地包括物理介质连接模块和物理编码子层模块。第二数量的频道中的每一个较高频道优选地还包括时钟管理单元，而第一数量的频道中的较低速频道优选地共享一个或多个时钟管理单元。

14. 发明申请

US20060012394A1 Programmable logic devices with multi-standard byte synchronization and channel alignment for communication 有权
公开(公告)号：US20060012394A1
公开(公告)日：2006-01-19
申请号：US11189209
申请日：2005-07-26
申请人： Ramanand Venkata , Chong Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong Lee , Rakesh Patel
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H04J3/1617 , H04J2203/0082 , H04J2203/0094
摘要： A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

15. 发明授权

US07292070B1 Programmable PPM detector 有权
标题翻译：可编程PPM探测器
公开(公告)号：US07292070B1
公开(公告)日：2007-11-06
申请号：US11200579
申请日：2005-08-09
申请人： Seungmyon Park , Ramanand Venkata , Chong Lee
发明人： Seungmyon Park , Ramanand Venkata , Chong Lee
IPC分类号： G01R23/02 , H03D3/00 , H03K9/06
CPC分类号： H03K19/1774 , H03K19/17744
摘要： A device such as a programmable logic device (“PLD”) includes circuitry for detecting the PPM frequency difference between two input clock signals. For example, this circuitry may accept a user-programmable PPM threshold value and output a signal when this threshold value is met.
摘要翻译：诸如可编程逻辑器件（“PLD”）的器件包括用于检测两个输入时钟信号之间的PPM频差的电路。例如，该电路可以接受用户可编程的PPM阈值，并且当满足该阈值时输出信号。

16. 发明申请

US20070188189A1 PROGRAMMABLE LOGIC DEVICE WITH SERIAL INTERCONNECT 有权
标题翻译：具有串行互连的可编程逻辑器件
公开(公告)号：US20070188189A1
公开(公告)日：2007-08-16
申请号：US11539006
申请日：2006-10-05
申请人： Ramanand Venkata , Rakesh Patel , Chong Lee
发明人： Ramanand Venkata , Rakesh Patel , Chong Lee
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17744 , H03K19/17784
摘要： In a programmable logic device, some or all of the parallel interconnect resources are replaced by serial interconnect resources within the device. Some or all of the functional blocks on the device are supplemented with serial interfaces. Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces may operate synchronously from a global device clock (such as a PLL). In some cases, serial interfaces that are provided in the input/output blocks for external signalling can be omitted because the serial interfaces in the functional blocks can take over the external serial interface function as well, although in those cases the serial interfaces in the functional blocks would have to be more complex because they would have to be able to operate asynchronously with external devices.
摘要翻译：在可编程逻辑器件中，部分或全部并行互连资源由器件内的串行互连资源代替。设备上的部分或全部功能块被补充有串行接口。尽管这使得功能块更加复杂，但它允许显着减少互连资源消耗的面积。这意味着设备功耗的显着降低。串行接口可以与全局设备时钟（例如PLL）同步工作。在某些情况下，可以省略输入/输出块中提供的用于外部信号的串行接口，因为功能块中的串行接口也可以接管外部串行接口功能，尽管在这些情况下，功能中的串行接口块将不得不更复杂，因为它们必须能够与外部设备异步操作。

17. 发明申请

US20060233172A1 Multiple data rates in programmable logic device serial interface 失效
公开(公告)号：US20060233172A1
公开(公告)日：2006-10-19
申请号：US11177034
申请日：2005-07-08
申请人： Ramanand Venkata , Chong Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong Lee , Rakesh Patel
IPC分类号： H04L12/28
CPC分类号： H03K19/17744
摘要： A serial interface for a programmable logic device can be operated according to various communications protocols and includes both a receiver portion and a transmitter portion. The receiver portion includes at least a word or byte alignment stage, a de-skew stage, a rate compensation or matching stage, a padded protocol decoder stage (e.g., 8B/10B decoder circuitry or 64B/66B decoder circuitry), a byte deserializer stage, a byte reorder stage, and a phase compensation stage. The transmitter portion includes at least a phase compensation stage, a byte deserializer stage, and a padded protocol encoder stage (e.g., an 8B/10B encoder circuitry or 64B/66B encoder circuitry). Each stage may have multiple occurrences of relevant circuitry. Selection circuitry, such as multiplexers, selects the appropriate stages, and circuitry within each stage, for the protocol being used.

18. 发明授权

US07366267B1 Clock data recovery with double edge clocking based phase detector and serializer/deserializer 有权
标题翻译：基于双边沿时钟的相位检测器和串行器/解串器的时钟数据恢复
公开(公告)号：US07366267B1
公开(公告)日：2008-04-29
申请号：US10059014
申请日：2002-01-29
申请人： Chong Lee , Ramanand Venkata
发明人： Chong Lee , Ramanand Venkata
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , H03K5/135 , H03M9/00 , H04L7/0337
摘要： A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). THE CDR circuitry is provided with a programmable serializer and/or deserializer that can support higher data clock rates than the highest clock rate associated with the reference clock signal or clock signal from a phase locked loop circuit.
摘要翻译：可编程逻辑器件（“PLD”）用可编程时钟数据恢复（“CDR”）电路进行增强，以允许PLD通过大量CDR信令协议中的任何一个进行通信。 CDR电路可以与PLD集成，或者它可以全部或部分地在单独的集成电路上。电路可能能够进行CDR输入，CDR输出或两者。 CDR能力可以与其他非CDR信令能力组合提供，例如非CDR低电压差分信号（“LVDS”）。 CDR电路配备有可编程串行器和/或解串器，其可以支持比与来自锁相环电路的参考时钟信号或时钟信号相关联的最高时钟速率更高的数据时钟速率。

19. 发明申请

US20070139232A1 Next generation 8B10B architecture 有权
公开(公告)号：US20070139232A1
公开(公告)日：2007-06-21
申请号：US11655797
申请日：2007-01-18
申请人： Ramanand Venkata , Rakesh Patel , Chong Lee
发明人： Ramanand Venkata , Rakesh Patel , Chong Lee
IPC分类号： H03M7/00
CPC分类号： G06F13/385
摘要： Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.

20. 发明授权

US07071726B1 Selectable dynamic reconfiguration of programmable embedded IP 失效
标题翻译：可编程嵌入式IP的可选择动态重新配置
公开(公告)号：US07071726B1
公开(公告)日：2006-07-04
申请号：US11005390
申请日：2004-12-01
申请人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata , Binh Ton
发明人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata , Binh Ton
IPC分类号： H03K19/00
CPC分类号： H03K19/17752 , H03K19/17732 , H03K19/17736 , H03K19/17744
摘要： Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the invention may include at least two different signal paths between the PLD core fabric and embedded IP building blocks. Either one, or both, of these two paths may be used for configuration and/or implementation of the embedded IP building blocks.
摘要翻译：提供了PLD的核心PLD结构与驻留在其中的嵌入式IP构建块之间的改进的通信和改进的通信接口。根据本发明的电路可以包括PLD核心结构和嵌入式IP构建块之间的至少两个不同的信号路径。这两个路径中的一个或两者可以用于嵌入式IP构建块的配置和/或实现。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式