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11. 发明申请

US20060065914A1 STRUCTURE AND METHOD FOR MAKING STRAINED CHANNEL FIELD EFFECT TRANSISTOR USING SACRIFICIAL SPACER 有权
公开(公告)号：US20060065914A1
公开(公告)日：2006-03-30
申请号：US10711637
申请日：2004-09-29
申请人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner Rausch , Tsutomu Sato , Henry Utomo
发明人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner Rausch , Tsutomu Sato , Henry Utomo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/28052 , H01L21/28079 , H01L21/7624 , H01L29/1045 , H01L29/165 , H01L29/4933 , H01L29/495 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

12. 发明申请

US20100187636A1 METHOD TO INCREASE STRAIN ENHANCEMENT WITH SPACERLESS FET AND DUAL LINER PROCESS 审中-公开
标题翻译：用不间断FET和双线性过程增加应变增强的方法
公开(公告)号：US20100187636A1
公开(公告)日：2010-07-29
申请号：US12754939
申请日：2010-04-06
申请人： Haining S. Yang , Siddhartha Panda
发明人： Haining S. Yang , Siddhartha Panda
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L27/1203 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a method of fabricating the same in which strain enhancement is achieved for both nFET and pFET devices is provided. In particular, the present invention provides at least one spacerless FET for stronger strain enhancement and defect reduction. The at least one spacerless FET can be a pFET, an nFET, or a combination thereof, with spacerless pFETs being particularly preferred since pFETs are generally fabricated to have a greater width than nFETs. The at least one spacerless FET allows to provide a stress inducing liner in closer proximity to the device channel than prior art structures including FETs having spacers. The spacerless FET is achieved without negatively affecting the resistance of the corresponding silicided source/drain diffusion contacts, which do not encroach underneath the spacerless FET.
摘要翻译：提供半导体结构及其制造方法，其中对nFET和pFET器件实现应变增强。特别地，本发明提供了用于更强应变增强和缺陷减少的至少一个无间隔型FET。至少一个无衬垫FET可以是pFET，nFET或其组合，其中无间隙pFET是特别优选的，因为pFET通常制造成具有比nFET更大的宽度。至少一个无间隔FET允许提供比包括具有间隔物的FET的现有技术结构更靠近器件沟道的应力诱导衬垫。实现了无间隔FET，而不会不利地影响相应的硅化物源极/漏极扩散触点的电阻，其不会侵入无间隔FET的下方。

13. 发明授权

US07645656B2 Structure and method for making strained channel field effect transistor using sacrificial spacer 有权
标题翻译：使用牺牲隔离层制造应变通道场效应晶体管的结构和方法
公开(公告)号：US07645656B2
公开(公告)日：2010-01-12
申请号：US11463777
申请日：2006-08-10
申请人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner A. Rausch , Tsutomu Sato , Henry K. Utomo
发明人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner A. Rausch , Tsutomu Sato , Henry K. Utomo
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/28052 , H01L21/28079 , H01L21/7624 , H01L29/1045 , H01L29/165 , H01L29/4933 , H01L29/495 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.
摘要翻译：提供场效应晶体管（“FET”），其包括覆盖衬底的单晶半导体区域的栅极堆叠，设置在所述栅极堆叠的侧壁上的一对第一间隔区，以及基本上由单个晶体半导体合金，其设置在栅叠层的相对侧上。每个半导体合金区域与栅极叠层隔开第一距离。 FET的源极区域和漏极区域至少部分地设置在半导体合金区域的相应半导体合金区域中，使得源极区域和漏极区域之间的距离与栅极叠层间隔开第二距离，第一间隔物，第二距离与第一距离不同。

14. 发明申请

US20090159934A1 FIELD EFFECT DEVICE WITH REDUCED THICKNESS GATE 有权
标题翻译：具有减小厚度门的场效应装置
公开(公告)号：US20090159934A1
公开(公告)日：2009-06-25
申请号：US12274758
申请日：2008-11-20
申请人： Ricky S. Amos , Wesley C. Natzle , Siddhartha Panda , Brian L. Tessier
发明人： Ricky S. Amos , Wesley C. Natzle , Siddhartha Panda , Brian L. Tessier
IPC分类号： H01L29/80 , H01L21/335
CPC分类号： H01L21/28097 , H01L29/66507 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.
摘要翻译：通过减薄栅电极来制造具有减小的栅极电容的半导体结构，以提供减小厚度的栅电极。在形成与栅电极相邻的间隔层之后，栅电极变薄。此外，间隔层的高度也可以减小。间隔层因此具有相对于延伸区域定位本征源极/漏极所需的增强的水平宽度，特别是相对于间隔物高度的增强的水平宽度。减薄厚度的栅电极可以被完全硅化以提供降低的栅极电阻。升高的源极/漏极层可以位于本征源极/漏极区域上。凸起的源极/漏极层可以具有比缩小的厚度栅电极高的顶表面。此外，隆起的源极/漏极层可以具有高于缩小的高度间隔层的顶表面。

15. 发明授权

US07525161B2 Strained MOS devices using source/drain epitaxy 有权
标题翻译：使用源极/漏极外延的应变MOS器件
公开(公告)号：US07525161B2
公开(公告)日：2009-04-28
申请号：US11669902
申请日：2007-01-31
申请人： Meikei Ieong , Xiao Hu Liu , Qiqing Christine Ouyang , Siddhartha Panda , Haizhou Yin
发明人： Meikei Ieong , Xiao Hu Liu , Qiqing Christine Ouyang , Siddhartha Panda , Haizhou Yin
IPC分类号： H01L29/94
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7848 , H01L29/78687
摘要： NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the source and the drain of the PMOS device is epitaxially grown of a material which causes a shift in the strain of the PMOS device channel in the compressive direction.
摘要翻译：公开了具有单独应变通道区域的NMOS和PMOS器件结构及其制造方法。 NMOS器件的源极和漏极由引起NMOS器件沟道在拉伸方向上的应变移动的材料外延生长。而PMOS器件的源极和漏极是外延生长的，这种材料导致PMOS器件沟道在压缩方向上的应变移动。

16. 发明授权

US07405436B2 Stressed field effect transistors on hybrid orientation substrate 有权
标题翻译：混合取向衬底上强调场效应晶体管
公开(公告)号：US07405436B2
公开(公告)日：2008-07-29
申请号：US11029797
申请日：2005-01-05
申请人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Oiging C. Ouyang , Siddhartha Panda
发明人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Oiging C. Ouyang , Siddhartha Panda
IPC分类号： H01L29/04 , H01L21/8238
CPC分类号： H01L29/045 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.
摘要翻译：提供了具有改进的载流子迁移率的半导体结构。半导体结构包括具有不同晶体取向的至少两个平坦表面的混合取向半导体衬底，以及位于不同结晶取向的每个平面上的至少一个CMOS器件，其中每个CMOS器件具有应力通道。本发明还提供了制造该方法的方法。一般来说，本发明的方法包括提供具有至少两个具有不同晶体取向的平面表面的混合取向衬底，以及在不同结晶取向的每个平面上形成至少一个CMOS器件，其中每个CMOS器件具有受压沟道。

17. 发明授权

US07344991B2 Method and apparatus for multilayer photoresist dry development 有权
公开(公告)号：US07344991B2
公开(公告)日：2008-03-18
申请号：US10640577
申请日：2003-08-14
申请人： Vaidyanathan Balasubramaniam , Koichiro Inazawa , Rich Wise , Arpan Mahorowala , Siddhartha Panda
发明人： Vaidyanathan Balasubramaniam , Koichiro Inazawa , Rich Wise , Arpan Mahorowala , Siddhartha Panda
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/0276 , A61M2025/024 , A61M2025/028 , H01L21/31138 , H01L21/31144
摘要： A method for etching an organic anti-reflective coating (ARC) layer on a substrate in a plasma processing system comprising: introducing a process gas comprising ammonia (NH3), and a passivation gas; forming a plasma from the process gas; and exposing the substrate to the plasma. The process gas can, for example, constitute NH3 and a hydrocarbon gas such as at least one of C2H4, CH4, C2H2, C2H6, C3H4, C3H6, C3H8, C4H6, C4H8, C4H10, C5H8, C5H10, C6H6, C6H10, and C6H12. Additionally, the process chemistry can further comprise the addition of helium. The present invention further presents a method for forming a bilayer mask for etching a thin film on a substrate, wherein the method comprises: forming the thin film on the substrate; forming an ARC layer on the thin film; forming a photoresist pattern on the ARC layer; and transferring the photoresist pattern to the ARC layer with an etch process using a process gas comprising ammonia (NH3), and a passivation gas.

18. 发明授权

US07256399B2 Non-destructive in-situ elemental profiling 失效
标题翻译：非破坏性原位元素分析
公开(公告)号：US07256399B2
公开(公告)日：2007-08-14
申请号：US10907591
申请日：2005-04-07
申请人： Siddhartha Panda , Michael R. Sievers , Richard S. Wise
发明人： Siddhartha Panda , Michael R. Sievers , Richard S. Wise
IPC分类号： G01N23/227
CPC分类号： G01N23/2273
摘要： A non-destructive in-situ elemental profiling of a layer in a set of layers method and system are disclosed. In one embodiment, a first emission of a plurality of photoelectrons is caused from the layer to be elementally profiled. An elemental profile of the layer is determined based on the emission. In another embodiment, a second emission of a plurality of photoelectrons is also received from the layer, and an elemental profile is determined by comparison of the resulting signals. A process that is altering the layer can then be controlled “on-the-fly” to obtain a desired material composition. Since the method can be employed in-situ and is non-destructive, it reduces turn around time and lowers wafer consumption. The invention also records the composition of all processed wafers, hence, removing the conventional statistical sampling problem.
摘要翻译：公开了一组层中的层的非破坏性原位元素分析方法和系统。在一个实施例中，多个光电子的第一次发射是从该层进行元素分析。基于发射确定层的元素分布。在另一个实施例中，也从该层接收多个光电子的第二次发射，并且通过比较所得到的信号来确定元素分布。然后可以“即时”控制改变层的方法以获得所需的材料组成。由于该方法可以原位使用并且是非破坏性的，所以可以减少周转时间并降低晶片消耗。本发明还记录了所有加工晶片的组成，因此，去除了常规统计抽样问题。

19. 发明申请

US20070108525A1 STRUCTURE AND METHOD TO INCREASE STRAIN ENHANCEMENT WITH SPACERLESS FET AND DUAL LINER PROCESS 失效
标题翻译：用不间断FET和双线性过程增加应变增强的结构和方法
公开(公告)号：US20070108525A1
公开(公告)日：2007-05-17
申请号：US11164193
申请日：2005-11-14
申请人： Haining Yang , Siddhartha Panda
发明人： Haining Yang , Siddhartha Panda
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/823807 , H01L21/823864 , H01L27/1203 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a method of fabricating the same in which strain enhancement is achieved for both nFET and pFET devices is provided. In particular, the present invention provides at least one spacerless FET for stronger strain enhancement and defect reduction. The at least one spacerless FET can be a pFET, an nFET, or a combination thereof, with spacerless pFETs being particularly preferred since pFETs are generally fabricated to have a greater width than nFETs. The at least one spacerless FET allows to provide a stress inducing liner in closer proximity to the device channel than prior art structures including FETs having spacers. The spacerless FET is achieved without negatively affecting the resistance of the corresponding silicided source/drain diffusion contacts, which do not encroach underneath the spacerless FET.
摘要翻译：提供半导体结构及其制造方法，其中对nFET和pFET器件实现应变增强。特别地，本发明提供了用于更强应变增强和缺陷减少的至少一个无间隔型FET。至少一个无衬垫FET可以是pFET，nFET或其组合，其中无间隙pFET是特别优选的，因为pFET通常制造成具有比nFET更大的宽度。至少一个无间隔FET允许提供比包括具有间隔物的FET的现有技术结构更靠近器件沟道的应力诱导衬垫。实现了无间隔FET，而不会不利地影响相应的硅化物源极/漏极扩散触点的电阻，其不会侵入无间隔FET的下方。

20. 发明申请

US20060037940A1 Apparatus and method for shielding a wafer from charged particles during plasma etching 失效
标题翻译：在等离子体蚀刻期间屏蔽晶片与带电粒子的装置和方法
公开(公告)号：US20060037940A1
公开(公告)日：2006-02-23
申请号：US11260375
申请日：2005-10-28
申请人： Hongwen Yan , Brian Ji , Siddhartha Panda , Richard Wise , Bomy Chen
发明人： Hongwen Yan , Brian Ji , Siddhartha Panda , Richard Wise , Bomy Chen
IPC分类号： C23F1/00 , H01L21/306
CPC分类号： H01J37/32623 , H01J37/3266
摘要： A plasma etching system having a wafer chuck with a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles. The magnetic field is parallel with the wafer, and is strongest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer acquires a positive charge, and ions are deflected by electrostatic repulsion. Neutral species are allowed through the magnetic field, and they collide with the wafer. Neutral species generally provide more isotropic and material-selective etching than charged particles, so the present magnetic field tends to increase etch isotropy and material selectivity. Also, the magnetic field can protect the wafer from seasoning processes designed to clean unwanted films from the chamber surface as seasoning processes typically rely on etching by charged particles.
摘要翻译：一种等离子体蚀刻系统，其具有带有磁体的晶片卡盘，该磁体在晶片上施加磁场以将晶片免受带电粒子的影响。磁场与晶片平行，并且在晶片表面附近最强。磁场可以是直的或圆形的。在操作中，电子通过洛伦兹力从晶片偏转，晶片获得正电荷，离子被静电排斥偏转。允许中性物质通过磁场，并且它们与晶片碰撞。中性物质通常提供比带电粒子更多的各向同性和材料选择性蚀刻，因此目前的磁场倾向于增加蚀刻各向同性和材料选择性。此外，由于调味过程通常依赖于带电粒子的蚀刻，所以磁场可以保护晶片免受调节过程的调节过程，以便从室表面清洁不需要的膜。

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