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11. 发明授权

US07437537B2 Methods and apparatus for predicting unaligned memory access 有权
标题翻译：用于预测未对齐内存访问的方法和装置
公开(公告)号：US07437537B2
公开(公告)日：2008-10-14
申请号：US11062221
申请日：2005-02-17
申请人： Jeffrey Todd Bridges , Victor Roberts Augsburg , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Jeffrey Todd Bridges , Victor Roberts Augsburg , James Norris Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/30043 , G06F9/30145 , G06F9/30189 , G06F9/3824 , G06F9/3832 , G06F9/3855
摘要： In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the effective address generation of the memory access instruction. The additional micro-operation accesses the memory falling across a predetermined address boundary. Predicting the misalignment and generating a micro-operation early in the pipeline ensures that sufficient pipeline control resources are available to generate and track the additional micro-operation, avoiding a pipeline flush if the resources are not available at the time of effective address generation. The misalignment prediction may employ known conditional branch prediction techniques, such as a flag, a bimodal counter, a local predictor, a global predictor, and combined predictors. A misalignment predictor may be enabled or biased by a memory access instruction flag or misaligned instruction type.
摘要翻译：在指令执行流水线中，预测存储器访问指令的未对准。基于该预测，在存储器访问指令的有效地址生成之前在流水线中生成附加的微操作。附加的微操作访问落在预定地址边界上的存储器。预测未对准并在管道早期生成微操作确保足够的流水线控制资源可用于生成和跟踪附加的微操作，如果资源在有效地址生成时不可用，则避免管道冲洗。不对准预测可以使用已知的条件分支预测技术，例如标志，双模计数器，局部预测器，全局预测器和组合预测器。未对准预测器可能被存储器访问指令标志或未对准指令类型使能或偏置。

12. 发明授权

US07366869B2 Method and system for optimizing translation lookaside buffer entries 有权
标题翻译：优化翻译后备缓冲区条目的方法和系统
公开(公告)号：US07366869B2
公开(公告)日：2008-04-29
申请号：US11083691
申请日：2005-03-17
申请人： Thomas Andrew Sartorius , Jeffrey Todd Bridges , James Norris Dieffenderfer , Victor Roberts Augsburg
发明人： Thomas Andrew Sartorius , Jeffrey Todd Bridges , James Norris Dieffenderfer , Victor Roberts Augsburg
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/652
摘要： A system for optimizing translation lookaside buffer entries is provided. The system includes a translation lookaside buffer configured to store a number of entries, each entry having a size attribute, each entry referencing a corresponding page, and control logic configured to modify the size attribute of an existing entry in the translation lookaside buffer if a new page is contiguous with an existing page referenced by the existing entry. The existing entry after having had its size attribute modified references a consolidated page comprising the existing page and the new page.
摘要翻译：提供了一种用于优化翻译后备缓冲区条目的系统。该系统包括翻译后备缓冲器，其被配置为存储多个条目，每个条目具有大小属性，每个条目引用对应的页面，以及控制逻辑，被配置为修改翻译后备缓冲器中现有条目的大小属性，如果新的页面与现有条目引用的现有页面是连续的。修改其大小属性后的现有条目引用包含现有页面和新页面的合并页面。

13. 发明申请

US20060259669A1 Latency insensitive FIFO signaling protocol 有权
标题翻译：延迟不敏感的FIFO信令协议
公开(公告)号：US20060259669A1
公开(公告)日：2006-11-16
申请号：US11128135
申请日：2005-05-11
申请人： Kenneth Alan Dockser , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Robert Douglas Clancy , Thomas Andrew Sartorius
发明人： Kenneth Alan Dockser , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Robert Douglas Clancy , Thomas Andrew Sartorius
IPC分类号： G06F13/38
CPC分类号： G06F13/4059 , G06F5/06 , G06F2205/126
摘要： Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.
摘要翻译：来自以第一数据速率运行的源域的数据被传送到以不同数据速率工作的另一个域中的FIFO。 FIFO在传输到宿之前缓冲数据以进一步处理或存储。源端计数器跟踪FIFO中可用的空间。在公开的示例中，初始计数器值对应于FIFO深度。响应于来自源域的数据就绪信号，计数器无延迟地递减。响应于来自接收器域的信令从FIFO读取数据，计数器递增。因此，增量受到域之间的信令等待时间的限制。当计数器指示FIFO已满时，源可能再发送一次数据。数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。

14. 发明授权

US07210024B2 Conditional instruction execution via emissary instruction for condition evaluation 有权
标题翻译：有条件的指令通过使用指令执行条件评估
公开(公告)号：US07210024B2
公开(公告)日：2007-04-24
申请号：US11055919
申请日：2005-02-10
申请人： Michael Scott McIlvaine , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Michael Scott McIlvaine , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/30072 , G06F9/3017 , G06F9/30181 , G06F9/3824 , G06F9/3826
摘要： Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the condition and an unconditional base instruction operative to perform the operation. The emissary instruction is executed, while the base instruction is halted. The emissary instruction evaluates the condition and reports the condition evaluation back to the base instruction. Based on the condition evaluation, the base instruction is either launched into the pipeline for execution, or it is discarded (or a NOP, or null instruction, substituted for it). In either case, the dependencies of following instructions may be resolved.
摘要翻译：通过转换条件指令来简化危险检测，条件指令可操作以在满足条件的情况下执行操作到可操作以评估条件的执行指令和用于执行操作的无条件基准指令。在基本指令停止的情况下执行执行指令。使者指令评估条件并将条件评估报告回基本指令。基于条件评估，基本指令要么被启动到管道中才能执行，要么被丢弃（或者一个NOP或者空的指令代替它）。在任一情况下，可以解决以下指令的依赖性。

15. 发明授权

US07366877B2 Speculative instruction issue in a simultaneously multithreaded processor 失效
标题翻译：同时多线程处理器中的推测性指令问题
公开(公告)号：US07366877B2
公开(公告)日：2008-04-29
申请号：US10664384
申请日：2003-09-17
申请人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Michael Scott McIlvaine , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Michael Scott McIlvaine , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3826 , G06F9/3851
摘要： A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.
摘要翻译：一种用于优化微处理器中能够同时处理多个指令线程的吞吐量的方法。在输入缓冲器和微处理器的流水线之间提供指令发生逻辑。指令问题逻辑根据当指令到达需要的流水线中的阶段时，基于所需操作数将可用的概率来推测来自给定线程的指令。如果当前流水线条件表明指令需要在共享资源中停止以等待操作数的重要概率，则指令的发出被阻止。一旦指令停顿的概率低于某个阈值，则根据当前流水线条件，允许发出指令。

16. 发明授权

US5996092A System and method for tracing program execution within a processor before and after a triggering event 失效
标题翻译：在触发事件之前和之后跟踪处理器内的程序执行的系统和方法
公开(公告)号：US5996092A
公开(公告)日：1999-11-30
申请号：US760553
申请日：1996-12-05
申请人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas K. Collopy , James N. Dieffenderfer , Thomas Andrew Sartorius
发明人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas K. Collopy , James N. Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F11/34 , G06F11/30
CPC分类号： G06F11/3466
摘要： A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. Tracing of the program flow includes tracing instructions both before and after a trace triggering event. The implementation of periodic synchronizing events enables the tracing of instructions occurring before and after a triggering event.
摘要翻译：一种用于在具有嵌入式高速缓冲存储器的处理器内跟踪程序代码的系统和方法。非侵入性跟踪技术最大限度地减少了要在外部广播的跟踪信息的需要。跟踪技术监视来自代码的正常执行流的指令流程的变化。跟踪技术监控处理器分支目标寄存器内容的更新，以便监视代码的分支目标流。跟踪程序流程包括跟踪触发事件之前和之后的跟踪指令。周期性同步事件的实现使得能够跟踪在触发事件之前和之后发生的指令。

17. 发明授权

US06948053B2 Efficiently calculating a branch target address 失效
标题翻译：有效地计算分支目标地址
公开(公告)号：US06948053B2
公开(公告)日：2005-09-20
申请号：US10082144
申请日：2002-02-25
申请人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Thomas Philip Speier
发明人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Thomas Philip Speier
IPC分类号： G06F9/00 , G06F9/32 , G06F9/38
CPC分类号： G06F9/322 , G06F9/324 , G06F9/3804
摘要： A method and system for calculating a branch target address. Upon fetching a branch instruction from memory, the n−1 lower order bits of the branch target address may be pre-calculated and stored in the branch instruction prior to storing the branch instruction in the instruction cache. Upon retrieving the branch instruction from the instruction cache, the upper order bits of the branch target address may be recovered using the sign bit and the carry bit stored in the branch instruction. The sign bit and the carry bit may be used to select one of three possible upper-order bit value combinations of the branch target address. The selected upper-order bit value combination may then be appended to the n−1 lower order bits of the branch target address to form the complete branch target address.
摘要翻译：一种用于计算分支目标地址的方法和系统。在从存储器取出分支指令时，可以在将转移指令存储在指令高速缓存中之前将分支目标地址的n-1个较低位进行预先计算并存储在转移指令中。在从指令高速缓存中检索分支指令时，可以使用分支指令中存储的符号位和进位位来恢复分支目标地址的高位。符号位和进位位可用于选择分支目标地址的三个可能的高位位组合之一。然后可以将所选择的高位比特值组合附加到分支目标地址的n-1个较低位，以形成完整的分支目标地址。

18. 发明授权

US07152155B2 System and method of correcting a branch misprediction 有权
标题翻译：校正分支错误预测的系统和方法
公开(公告)号：US07152155B2
公开(公告)日：2006-12-19
申请号：US11061981
申请日：2005-02-18
申请人： Michael Scott McIlvaine , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
发明人： Michael Scott McIlvaine , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3861
摘要： When a branch misprediction in a pipelined processor is discovered, if the mispredicted branch instruction is not the last uncommitted instruction in the pipelines, older uncommitted instructions are checked for dependency on a long latency operation. If one is discovered, all uncommitted instructions are flushed from the pipelines without waiting for the dependency to be resolved. The branch prediction is corrected, and the branch instruction and all flushed instructions older than the branch instruction are re-fetched and executed.
摘要翻译：当发现流水线处理器中的分支错误预测时，如果错误的分支指令不是管道中的最后一条未提交的指令，则会检查较长的未提交的指令对长时间延迟操作的依赖性。如果被发现，所有未提交的指令都将从管道中刷新，而不必等待解决依赖关系。纠正分支预测，并且重新获取并执行分支指令和比分支指令更早的所有刷新指令。

19. 发明授权

US07698536B2 Method and system for providing an energy efficient register file 有权
标题翻译：提供能量效率寄存器文件的方法和系统
公开(公告)号：US07698536B2
公开(公告)日：2010-04-13
申请号：US11201542
申请日：2005-08-10
申请人： James Norris Dieffenderfer , Thomas Andrew Sartorius , Jeffrey Todd Bridges , Michael Scott McIlvaine , Gregory Christopher Burda
发明人： James Norris Dieffenderfer , Thomas Andrew Sartorius , Jeffrey Todd Bridges , Michael Scott McIlvaine , Gregory Christopher Burda
IPC分类号： G06F9/00
CPC分类号： G06F9/30105 , G06F9/30141
摘要： A register file is disclosed. The register file includes a plurality of registers and a decoder. The decoder may be configured to receive an address for any one of the registers, and disable a read operation to the addressed register if data in the addressed register is invalid.
摘要翻译：公开了一种寄存器文件。寄存器文件包括多个寄存器和解码器。解码器可以被配置为接收任何一个寄存器的地址，并且如果寻址的寄存器中的数据无效，则禁止对寻址的寄存器的读取操作。

20. 发明授权

US07376815B2 Methods and apparatus to insure correct predecode 有权
标题翻译：确保正确预解码的方法和装置
公开(公告)号：US07376815B2
公开(公告)日：2008-05-20
申请号：US11066957
申请日：2005-02-25
申请人： Rodney Wayne Smith , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
发明人： Rodney Wayne Smith , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F8/447 , G06F9/382
摘要： Techniques for ensuring a synchronized predecoding of an instruction string are disclosed. The instruction string contains instructions from a variable length instruction set and embedded data. One technique includes defining a granule to be equal to the smallest length instruction in the instruction set and defining the number of granules that compose the longest length instruction in the instruction set to be MAX. The technique further includes determining the end of an embedded data segment, when a program is compiled or assembled into the instruction string and inserting a padding of length, MAX−1, into the instruction string to the end of the embedded data. Upon predecoding of the padded instruction string, a predecoder maintains synchronization with the instructions in the padded instruction string even if embedded data is coincidentally encoded to resemble an existing instruction in the variable length instruction set.
摘要翻译：公开了用于确保指令串的同步预解码的技术。指令串包含来自可变长度指令集和嵌入数据的指令。一种技术包括定义一个等于指令集中最小长度指令的粒子，并将构成指令集中最长指令的粒子数定义为MAX。该技术还包括当程序被编译或组装成指令串并将长度为MAX-1的填充插入到嵌入数据的结尾的指令串中时，确定嵌入数据段的结束。在预编译填充指令串时，即使嵌入数据被巧合地编码成类似于可变长度指令集中的现有指令，预解码器也保持与填充指令串中的指令的同步。

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