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11. 发明授权

US4959812A Electrically erasable programmable read-only memory with NAND cell structure 失效
标题翻译：具有NAND单元结构的电可擦除可编程只读存储器
公开(公告)号：US4959812A
公开(公告)日：1990-09-25
申请号：US289702
申请日：1988-12-27
申请人： Masaki Momodomi , Fujio Masuoka , Riichiro Shirota , Yasuo Itoh , Kazunori Ohuchi , Ryouhei Kirisawa
发明人： Masaki Momodomi , Fujio Masuoka , Riichiro Shirota , Yasuo Itoh , Kazunori Ohuchi , Ryouhei Kirisawa
IPC分类号： G11C17/00 , G11C16/04 , G11C16/16 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/16 , G11C16/0483
摘要： An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence. When data is written into a certain memory cell in the selected NAND cell block, a control gate of the certain memory cell is supplied with a voltage which is so high as to form a strong electric field to allow the tunneling of electrons between the floating gate of the memory cell and the well layer. Consequently, only the selected cell can be written into.

12. 发明授权

US4939690A Electrically erasable programmable read-only memory with NAND cell structure that suppresses memory cell threshold voltage variation 失效
标题翻译：具有NAND单元结构的电可擦除可编程只读存储器，可抑制存储单元阈值电压变化
公开(公告)号：US4939690A
公开(公告)日：1990-07-03
申请号：US290427
申请日：1988-12-27
申请人： Masaki Momodomi , Riichiro Shirota , Yasuo Itoh , Satoshi Inoue , Fujio Masuoka , Ryozo Nakayama , Ryouhei Kirisawa
发明人： Masaki Momodomi , Riichiro Shirota , Yasuo Itoh , Satoshi Inoue , Fujio Masuoka , Ryozo Nakayama , Ryouhei Kirisawa
IPC分类号： G11C16/04
CPC分类号： G11C16/0483
摘要： An erasable programmable read-only memory with NAND cell structure is disclosed which includes NAND cell blocks each of which has a selection transistor connected to a corresponding bit line and a series array of memory cell transistors. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data erase mode all the memory cells are simultaneously erased by applying a "H" level potential to the control gates of the memory cells and a "L" level potential to the bit lines. Prior to such a simultaneous erase, charges are removed from charge accumulation layers of the memory cells so that the threshold values of the memory cells are initialized. The threshold initialization is performed on the series-arrayed memory cell transistors in the NAND cell block in sequence.
摘要翻译：公开了具有NAND单元结构的可擦除可编程只读存储器，其包括NAND单元块，每个NAND单元具有连接到相应位线的选择晶体管和存储单元晶体管的串联阵列。每个单元晶体管具有浮置栅极和控制栅极。字线连接到单元晶体管的控制栅极。在数据擦除模式下，通过向存储单元的控制栅极施加“H”电平电位，并将位线的“L”电平电位同时擦除所有存储单元。在这种同时擦除之前，从存储器单元的电荷累积层去除电荷，使得存储单元的阈值被初始化。对NAND单元块中的串联存储单元晶体管依次执行阈值初始化。

13. 发明授权

US5597748A Method of manufacturing NAND type EEPROM 失效
标题翻译：制造NAND型EEPROM的方法
公开(公告)号：US5597748A
公开(公告)日：1997-01-28
申请号：US247589
申请日：1994-05-23
申请人： Masamichi Asano , Hiroshi Iwahashi , Ryouhei Kirisawa , Ryozo Nakayama , Satoshi Inoue , Riichiro Shirota , Tetsuo Endoh , Fujio Masuoka
发明人： Masamichi Asano , Hiroshi Iwahashi , Ryouhei Kirisawa , Ryozo Nakayama , Satoshi Inoue , Riichiro Shirota , Tetsuo Endoh , Fujio Masuoka
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11519 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.
摘要翻译：本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。浮动栅极部分地覆盖沟道区域。因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。多个存储单元串联连接以构成基本块。相邻的基本块由增强型MOS晶体管分开。在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

14. 发明授权

US5824583A Non-volatile semiconductor memory and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US5824583A
公开(公告)日：1998-10-20
申请号：US949819
申请日：1997-10-14
申请人： Masamichi Asano , Hiroshi Iwahashi , Ryouhei Kirisawa , Ryozo Nakayama , Satoshi Inoue , Riichiro Shirota , Tetsuo Endoh , Fujio Masuoka
发明人： Masamichi Asano , Hiroshi Iwahashi , Ryouhei Kirisawa , Ryozo Nakayama , Satoshi Inoue , Riichiro Shirota , Tetsuo Endoh , Fujio Masuoka
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11519 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.
摘要翻译：本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。浮动栅极部分地覆盖沟道区域。因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。多个存储单元串联连接以构成基本块。相邻的基本块由增强型MOS晶体管分开。在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

15. 发明授权

US5323039A Non-volatile semiconductor memory and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US5323039A
公开(公告)日：1994-06-21
申请号：US499342
申请日：1990-06-21
申请人： Masamichi Asano , Hiroshi Iwahashi , Ryouhei Kirisawa , Ryozo Nakayama , Satoshi Inoue , Riichiro Shirota , Tetsuo Endoh , Fujio Masuoka
发明人： Masamichi Asano , Hiroshi Iwahashi , Ryouhei Kirisawa , Ryozo Nakayama , Satoshi Inoue , Riichiro Shirota , Tetsuo Endoh , Fujio Masuoka
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/68
CPC分类号： H01L27/11519 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.
摘要翻译： PCT No.PCT / JP89 / 00942 Sec。 371 1990年6月21日第 102（e）日期1990年6月21日PCT提交1989年9月14日PCT公布。公开号WO90 / 04855 日期为1990年5月3日。本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。浮动栅极部分地覆盖沟道区域。因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。多个存储单元串联连接以构成基本块。相邻的基本块由增强型MOS晶体管分开。在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

16. 发明授权

US5831903A Electrically erasable programmable read-only memory with threshold value controller for data programming and method of programming the same 失效
标题翻译：电可擦除可编程只读存储器，具有用于数据编程的阈值控制器和编程方法
公开(公告)号：US5831903A
公开(公告)日：1998-11-03
申请号：US868138
申请日：1997-06-03
申请人： Kazunori Ohuchi , Tomoharu Tanaka , Yoshihisa Iwata , Yasuo Itoh , Masaki Momodomi , Fujio Masuoka
发明人： Kazunori Ohuchi , Tomoharu Tanaka , Yoshihisa Iwata , Yasuo Itoh , Masaki Momodomi , Fujio Masuoka
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/26 , G11C16/34 , G11C29/00 , G11C29/12 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/06
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3454
摘要： A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific basing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplied the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.
摘要翻译： NAND单元型电可擦除可编程只读存储器具有包含NAND单元单元的存储器阵列部分。每个NAND单元单元具有作为存储单元晶体管的浮栅型金属氧化物半导体场效应晶体管的串联阵列。存储器部分与控制门控制器，数据锁存电路，读出放大器部分和数据比较器相关联，其经由输出缓冲器连接到验证终止检测器。当在数据编程模式中将数据一次写入所选择的存储单元中时，将特定的基准电压施加到所选择的单元，以便验证所选存储单元的实际电数据写入条件。如果比较器检测到验证的写入条件不满意，则通过用选择的存储单元晶体管补偿所验证的写入条件的不满足的适当电压来额外提供所选择的单元来重复执行数据重写操作。

17. 发明授权

US5657270A Electrically erasable programmable read-only memory with threshold value controller for data programming 失效
标题翻译：电可擦除可编程只读存储器，具有用于数据编程的阈值控制器
公开(公告)号：US5657270A
公开(公告)日：1997-08-12
申请号：US376665
申请日：1995-01-23
申请人： Kazunori Ohuchi , Tomoharu Tanaka , Yoshihisa Iwata , Yasuo Itoh , Masaki Momodomi , Fujio Masuoka
发明人： Kazunori Ohuchi , Tomoharu Tanaka , Yoshihisa Iwata , Yasuo Itoh , Masaki Momodomi , Fujio Masuoka
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/26 , G11C16/34 , G11C29/00 , G11C29/12 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/06
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3454
摘要： A non-volatile semiconductor memory device including a plurality of bit lines; a plurality of word lines insulatively intersecting the bit lines; a memory cell array including a plurality of memory cells coupled to the bit lines and the word lines, each memory cell including a transistor with a charge storage portion; a plurality of programming circuits coupled to the memory cell array (i) for storing data which define whether or not write voltages are to be applied to respective of the memory cells, (ii) for selectively applying the write voltages to a part of the memory cells, which part is selected according to the data stored in the plurality of programing circuits, (iii) for determining actual written states of the memory cells, and (iv) for selectively modifying the stored data based on a predetermined logical relationship between the determined actual written states of the memory cells and the data stored in the plurality of programming circuits, thereby applying the write voltages only to memory cells which are not sufficiently written to achieve a predetermined written state.
摘要翻译：一种包括多个位线的非易失性半导体存储器件; 多个字线与位线绝对相交; 包括耦合到位线和字线的多个存储单元的存储单元阵列，每个存储单元包括具有电荷存储部分的晶体管; 耦合到存储单元阵列（i）的多个编程电路，用于存储定义是否将写入电压施加到存储单元的相应数据的数据，（ii）用于选择性地将写入电压施加到存储器的一部分单元，根据存储在多个编程电路中的数据选择该部分，（iii）用于确定存储单元的实际写入状态，以及（iv）基于所确定的预定逻辑关系来选择性地修改所存储的数据存储单元的实际写入状态和存储在多个编程电路中的数据，从而将写入电压仅施加到未被充分写入以实现预定写入状态的存储单元。

18. 发明授权

US5247480A Electrically erasable progammable read-only memory with nand cell blocks 失效
标题翻译：具有n个单元块的电可擦除可编程只读存储器
公开(公告)号：US5247480A
公开(公告)日：1993-09-21
申请号：US773723
申请日：1991-10-09
申请人： Yasuo Itoh , Masaki Momodomi , Yoshihisa Iwata , Tomoharu Tanaka , Fujio Masuoka
发明人： Yasuo Itoh , Masaki Momodomi , Yoshihisa Iwata , Tomoharu Tanaka , Fujio Masuoka
IPC分类号： G11C16/08 , G11C16/12 , G11C16/30
CPC分类号： G11C16/08 , G11C16/12 , G11C16/30
摘要： An electrically erasable programmable read-only memory has memory cell blocks, each of which has NAND type cell units associated with the bit lines respectively. Each cell unit has a series-circuit of floating gate type memory cell transistors and a selection transistor provided between the corresponding bit line and the series-circuit of memory cell transistors. A row decoder is provided in common to the memory cell blocks, for generating an "H" level voltage which is supplied to a selection gate control line connected to the selection transistor and to a selected word line or lines in a cell unit. A voltage boost circuit is provided for every memory cell block, for causing the "H" level voltage to increase up to a preselected potential level which is high enough to render the cell transistors conductive. The voltage boost circuit includes a first booster section for the selection gate control line, and a second section for the word lines. The second section operates in response to the output voltage of the first section.
摘要翻译：电可擦除可编程只读存储器具有存储单元块，每个存储单元块分别具有与位线相关联的NAND型单元单元。每个单元单元具有浮置型存储单元晶体管的串联电路和设置在相应位线和存储单元晶体管的串联电路之间的选择晶体管。向存储单元块共同地提供行解码器，用于产生提供给连接到选择晶体管的选择栅极控制线和单元单元中所选择的字线或线的“H”电平电压。为每个存储单元块提供升压电路，用于使“H”电平电压增加到足以使单元晶体管导通的预选电位电平。升压电路包括用于选择栅极控制线的第一升压部分和用于字线的第二部分。第二部分响应于第一部分的输出电压而工作。

19. 发明授权

US5517457A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5517457A
公开(公告)日：1996-05-14
申请号：US360289
申请日：1994-12-21
申请人： Koji Sakui , Hiroshi Nakamura , Tomoharu Tanaka , Masaki Momodomi , Fujio Masuoka , Takehiro Hasegawa
发明人： Koji Sakui , Hiroshi Nakamura , Tomoharu Tanaka , Masaki Momodomi , Fujio Masuoka , Takehiro Hasegawa
IPC分类号： G11C16/06 , G11C5/02 , G11C11/401 , G11C11/407 , G11C16/04 , G11C16/08 , G11C17/00 , G11C29/00 , G11C29/04 , H01L29/78 , G11C13/00
CPC分类号： G11C29/80 , G11C16/0416 , G11C16/0483 , G11C16/08 , G11C5/025
摘要： An NAND cell type EEPROM comprising a memory cell array wherein an NAND cell unit having a plurality of electrically rewritable memory cells is connected in series, and the NAND cell is formed on a semiconductor substrate in a matrix array, a plurality of control gate lines CG each provided to cross an NAND cell group of the same row, bit lines BL each provided to cross the NAND cell group of the same column, wherein driver circuit are provided at both sides of the memory cell array in a ratio of one to two NAND cell units so as to drive the control gate lines CG, the plurality of the control gate lines CG, provided to cross the NAND cell unit of the even row, is connected to the left driver circuit, and the plurality of the control gate lines CG, provided to cross the NAND cell unit of the odd row, is connected to the right driver circuit.
摘要翻译：包括存储单元阵列的NAND单元型EEPROM，其中具有多个电可重写存储单元的NAND单元单元串联连接，NAND单元形成在矩阵阵列的半导体基板上，多个控制栅线CG 每个被提供以跨过同一行的NAND单元组，每个位线BL被提供以跨过同一列的NAND单元组，其中驱动电路以一到两个NAND的比率设置在存储单元阵列的两侧单元单元以驱动控制栅极线CG，设置为跨越偶数行的NAND单元单元的多个控制栅极线CG连接到左侧驱动电路，并且多个控制栅极线CG 被提供以跨越奇数行的NAND单元单元连接到右驱动器电路。

20. 发明授权

US6081454A Electrically erasable programmable read-only memory with threshold value controller for data programming 失效
标题翻译：电可擦除可编程只读存储器，具有用于数据编程的阈值控制器
公开(公告)号：US6081454A
公开(公告)日：2000-06-27
申请号：US145466
申请日：1998-09-02
申请人： Kazunori Ohuchi , Tomoharu Tanaka , Yoshihisa Iwata , Yasuo Itoh , Masaki Momodomi , Fujio Masuoka
发明人： Kazunori Ohuchi , Tomoharu Tanaka , Yoshihisa Iwata , Yasuo Itoh , Masaki Momodomi , Fujio Masuoka
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/26 , G11C16/34 , G11C29/00 , G11C29/12 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/06
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3454
摘要： A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific biasing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplying the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.
摘要翻译： NAND单元型电可擦除可编程只读存储器具有包含NAND单元单元的存储器阵列部分。每个NAND单元单元具有作为存储单元晶体管的浮栅型金属氧化物半导体场效应晶体管的串联阵列。存储器部分与控制门控制器，数据锁存电路，读出放大器部分和数据比较器相关联，其经由输出缓冲器连接到验证终止检测器。当在数据编程模式下将数据一次写入所选择的存储单元中时，将特定的偏置电压施加到所选择的单元，从而验证所选存储单元的实际电数据写入状态。如果比较器检测到验证的写入条件不满意，则通过向所选择的单元格额外提供补偿所选择的存储单元晶体管中的验证的写入条件的不满足的适当电压来重复执行数据重写操作。

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