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11. 发明授权

US06836398B1 System and method of forming a passive layer by a CMP process 有权
标题翻译：通过CMP工艺形成钝化层的系统和方法
公开(公告)号：US06836398B1
公开(公告)日：2004-12-28
申请号：US10284769
申请日：2002-10-31
申请人： Ramkumar Subramanian , Jane V. Oglesby , Minh Van Ngo , Mark S. Chang , Sergey D. Lopatin , Angela T. Hui , Christopher F. Lyons , Patrick K. Cheung , Ashok M. Khathuria
发明人： Ramkumar Subramanian , Jane V. Oglesby , Minh Van Ngo , Mark S. Chang , Sergey D. Lopatin , Angela T. Hui , Christopher F. Lyons , Patrick K. Cheung , Ashok M. Khathuria
IPC分类号： H01G435
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , H01L21/3212 , H01L27/285 , H01L28/75
摘要： The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is performed on a semiconductor device in order to form a passive layer instead of performing a first CMP, followed by a deposition and a second CMP to form a passive layer. The reducing CMP process utilizes a slurry that includes a reducing chemistry that forms the passive layer in a dish region of an electrode. Thus, the passive layer is formed in conjunction with the reducing CMP process utilized for forming the electrode.
摘要翻译：本发明提供了通过平坦化工艺有助于形成半导体器件的系统和方法。本发明利用通常在化学机械平面化（CMP）工艺中发生的凹陷效应。在半导体器件上进行还原CMP工艺以形成无源层，而不是执行第一CMP，随后进行沉积和第二CMP以形成钝化层。还原CMP方法利用包含在电极的盘区域中形成钝化层的还原化学物质的浆料。因此，钝化层与用于形成电极的还原CMP工艺结合形成。

12. 发明授权

US06812077B1 Method for patterning narrow gate lines 失效
标题翻译：窄栅极线图案的制作方法
公开(公告)号：US06812077B1
公开(公告)日：2004-11-02
申请号：US10299433
申请日：2002-11-19
申请人： Darin Chan , Douglas J. Bonser , Mark S. Chang
发明人： Darin Chan , Douglas J. Bonser , Mark S. Chang
IPC分类号： H01L2100
CPC分类号： H01L21/32105 , H01L21/28088 , H01L21/28123
摘要： Patterning of a gate line is terminated prior to etching completely through the conductive layer from which it is patterned. Surfaces of the conductive layer are then reacted in a reactive atmosphere, and the reacted surfaces are removed, creating a narrow gate line. The protection provided by the remaining portion of the conductive layer during reaction protects the lower corners of the patterned feature from undercutting growth of reacted material. Alternatively, a gate line is patterned from a multi-layered conductive structure that includes a lower conductive layer and an upper conductive layer that exhibits higher reactivity in a reactive atmosphere than the lower layer. The upper layer is patterned and then the structure is reacted in the reactive atmosphere. Reacted portions of the upper layer are then removed and the lower layer is patterned in a self-aligned manner to complete the formation of a gate line and gate insulator.
摘要翻译：在蚀刻完全通过图案化的导电层之前终止栅极线的图案化。然后在反应性气氛中使导电层的表面反应，除去反应的表面，产生窄的栅极线。在反应期间由导电层的剩余部分提供的保护保护图案化特征的下角部不被反应材料的底切生长。或者，栅极线从包括下导电层和上导电层的多层导电结构图案化，反应性气氛中的反应性比下层高。上层被图案化，然后结构在反应性气氛中反应。然后去除上层的反应部分，并且以自对准方式图案化下层，以完成栅极线和栅极绝缘体的形成。

13. 发明授权

US06750127B1 Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance 有权
标题翻译：使用具有改善的耐蚀性的非晶碳制造半导体器件的方法
公开(公告)号：US06750127B1
公开(公告)日：2004-06-15
申请号：US10367407
申请日：2003-02-14
申请人： Mark S. Chang , Darin Chan , Chih Yuh Yang , Lu You , Scott A. Bell , Srikanteswara Dakshina-Murthy , Douglas J. Bonser
发明人： Mark S. Chang , Darin Chan , Chih Yuh Yang , Lu You , Scott A. Bell , Srikanteswara Dakshina-Murthy , Douglas J. Bonser
IPC分类号： H01L213205
CPC分类号： H01L21/32139 , H01L21/0332 , H01L21/0337
摘要： An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides improved pattern transfer accuracy compared to conventional undoped amorphous carbon.
摘要翻译：注入一个或多个掺杂剂的无定形碳层，其增强无定形碳对通常用于蚀刻多晶硅的蚀刻剂如氯和HBr的蚀刻电阻率。这样的层可以被图案化以形成用于蚀刻多晶硅的手掩模，其与常规未掺杂的无定形碳相比提供改进的图案转印精度。

14. 发明授权

US06642148B1 RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist 失效
标题翻译： RELACS收缩方法应用于使用化学放大DUV型光致抗蚀剂的LDD或埋入式位线植入物的单面抗蚀剂掩模
公开(公告)号：US06642148B1
公开(公告)日：2003-11-04
申请号：US10126326
申请日：2002-04-19
申请人： Kouros Ghandehari , Emmanuil H. Lingunis , Mark S. Chang , Angela Hui , Scott Bell , Jusuke Ogura
发明人： Kouros Ghandehari , Emmanuil H. Lingunis , Mark S. Chang , Angela Hui , Scott Bell , Jusuke Ogura
IPC分类号： H01L21302
CPC分类号： H01L29/6659 , H01L21/0274 , H01L21/31144 , H01L21/743 , H01L27/112 , H01L27/11521 , H01L27/11568
摘要： The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The semiconductor substrate is doped with a first dopant, using the first masking pattern as a doping mask, thereby forming a first dopant region in the semiconductor substrate underlying the first opening. The first masking pattern is swelled to decrease the first lateral dimension of the first opening to a second lateral dimension. The semiconductor substrate is then doped with a second dopant, using the swelled first masking pattern as a doping mask, thereby forming a second dopant region in the semiconductor substrate, and furthermore defining a graded junction within the semiconductor substrate.
摘要翻译：本发明一般涉及一种在半导体衬底内形成渐变结的方法。在半导体衬底上形成第一掩模图案，其具有由第一横向尺寸表征的第一开口。半导体衬底掺杂有第一掺杂剂，使用第一掩模图案作为掺杂掩模，由此在第一开口下面的半导体衬底中形成第一掺杂区域。第一掩模图案被膨胀以将第一开口的第一横向尺寸减小到第二横向尺寸。然后使用膨胀的第一掩模图案作为掺杂掩模，然后用半导体衬底掺杂第二掺杂剂，从而在半导体衬底中形成第二掺杂区，并且还限定半导体衬底内的渐变结。

15. 发明授权

US06400030B1 Self-aligning vias for semiconductors 有权
标题翻译：半导体自对准通孔
公开(公告)号：US06400030B1
公开(公告)日：2002-06-04
申请号：US09583817
申请日：2000-05-30
申请人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
发明人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
IPC分类号： H01L2348
CPC分类号： H01L21/76897 , H01L21/76802
摘要： An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. The stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.
摘要翻译：具有半导体器件的集成电路通过镶嵌在器件上方的第一氧化物层中的第一导电沟道连接。在第一沟道和第一氧化物层上顺序地沉积有终止氮化物层，通孔氧化物层，通路氮化物层和通路保护层。通孔抗蚀剂被光刻显影，具有大于通道宽度的矩形横截面通孔，并且通孔氮化物层被蚀刻到矩形横截面。第二沟道氧化物层和第二沟道抗蚀剂依次沉积在通孔氮化物层和暴露的通孔氧化物层上。第二通道抗蚀剂用第二通道光刻显影，并且各向异性氧化物蚀刻将第二通道和矩形盒通孔蚀刻到固定氮化物层。阻挡氮化物层以矩形通孔结构进行氮化蚀刻，并且导电材料被镶嵌到第二通道中，并且通孔被化学机械抛光以形成两个通道级之间的互连。

16. 发明授权

US5945352A Method for fabrication of shallow isolation trenches with sloped wall profiles 失效
标题翻译：用于制造具有倾斜壁型材的浅隔离沟槽的方法
公开(公告)号：US5945352A
公开(公告)日：1999-08-31
申请号：US994710
申请日：1997-12-19
申请人： Hung-Sheng Chen , Mark S. Chang
发明人： Hung-Sheng Chen , Mark S. Chang
IPC分类号： H01L21/308 , H01L21/762 , H01L21/302
CPC分类号： H01L21/76237 , H01L21/3085 , H01L21/3086 , H01L21/76232 , Y10S148/05
摘要： The present invention provides a method for fabricating shallow isolation trenches with sloped walls in semiconductor wafers. The method uses a conformal polysilicon layer to form an etch barrier over trench regions in a semiconductor substrate. This etch barrier has areas of varying thickness. The thickest areas of the etch barrier are located on the edges of trench structures and slow the etch process in the underlying substrate. The thinner regions of the etch barrier do not impede the etch process to as great an extent. This etch rate differential causes a sloped trench wall profile. The isolation trenches are completed by filling the surface with dielectric materials then planarizing.
摘要翻译：本发明提供一种用于在半导体晶片中制造具有倾斜壁的浅隔离沟槽的方法。该方法使用共形多晶硅层在半导体衬底中的沟槽区域上形成蚀刻势垒。该蚀刻屏障具有不同厚度的区域。蚀刻阻挡层的最厚区域位于沟槽结构的边缘上并减缓下面的衬底中的蚀刻过程。蚀刻阻挡层的较薄区域不会将蚀刻过程阻碍到很大的程度。该蚀刻速率差异导致倾斜的沟槽壁轮廓。通过用介电材料填充表面然后平坦化来完成隔离沟槽。

17. 发明授权

US5550405A Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS 失效
标题翻译：用于实现生产有价值，低电介质，低互连电阻和高性能ICS的加工技术
公开(公告)号：US5550405A
公开(公告)日：1996-08-27
申请号：US360856
申请日：1994-12-21
申请人： Robin W. Cheung , Mark S. Chang
发明人： Robin W. Cheung , Mark S. Chang
IPC分类号： H01L21/28 , H01L21/027 , H01L21/768 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53242 , H01L23/53228 , H01L23/53238 , H01L23/53252 , H01L23/5329 , H01L2924/0002 , Y10S148/10 , Y10S148/106 , Y10S438/95 , Y10S438/951
摘要： The interconnects in a semiconductor device contacting metal lines comprise a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative thereof. A tri-layer resist structure is used, together with a lift-off process, to form the interconnects. The low dielectric constant material provides a diffusion barrier to the diffusion of the low resistance metal. The tri-layer resist comprises a first layer of a dissolvable polymer, a second layer of a hard mask material, and a third layer of a resist material. The resulting structure provides an integrated circuit with increased speed and ease of fabrication.
摘要翻译：接触金属线的半导体器件中的互连包括诸如铜，金，银或铂的低电阻金属，并且由具有低介电常数的材料例如苯并环丁烯或其衍生物分离。使用三层抗蚀剂结构以及剥离工艺来形成互连。低介电常数材料为低电阻金属的扩散提供扩散阻挡层。三层抗蚀剂包括可溶解聚合物的第一层，硬掩模材料的第二层和抗蚀剂材料的第三层。所得到的结构提供了具有增加的速度和易于制造的集成电路。

18. 发明授权

US4370405A Multilayer photoresist process utilizing an absorbant dye 失效
标题翻译：利用吸收剂染料的多层光刻胶工艺
公开(公告)号：US4370405A
公开(公告)日：1983-01-25
申请号：US248927
申请日：1981-03-30
申请人： Michael M. O'Toole , En-Den D. Liu , Mark S. Chang
发明人： Michael M. O'Toole , En-Den D. Liu , Mark S. Chang
IPC分类号： H01L21/302 , G03F7/09 , H01L21/027 , H01L21/30 , H01L21/3065 , G03C5/00
CPC分类号： G03F7/094 , H01L21/30
摘要： An improved photoetch technique is presented of the multilayer resist type wherein a thin top layer of resist and a thick planarizing layer are deposited on a substrate and the thin layer is exposed and developed to produce a patterned resist layer. The improvement involves dissolving a suitable dye in a layer between the thin top layer and the substrate. The dye is preferably selected to absorb light of the wavelengths used to expose the top layer but does not interfere with processing of the other layers.
摘要翻译：提出了一种改进的光刻技术，其中抗蚀剂的薄顶层和厚的平坦化层沉积在衬底上，并且薄层被曝光和显影以产生图案化的抗蚀剂层。该改进涉及将合适的染料溶解在薄顶层和基底之间的层中。优选选择染料以吸收用于暴露顶层的波长的光，但不影响其它层的处理。

19. 发明授权

US08183619B1 Method and system for providing contact to a first polysilicon layer in a flash memory device 有权
公开(公告)号：US08183619B1
公开(公告)日：2012-05-22
申请号：US09539458
申请日：2000-03-30
申请人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko
发明人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/76816 , H01L27/115
摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

20. 发明申请

US20080142873A1 INTEGRATED CIRCUIT SYSTEM WITH METAL AND SEMI-CONDUCTING GATE 有权
标题翻译：具有金属和半导体门的集成电路系统
公开(公告)号：US20080142873A1
公开(公告)日：2008-06-19
申请号：US11611856
申请日：2006-12-16
申请人： Angela T. Hui , Mark S. Chang , Kuo-Tung Chang , Scott A. Bell
发明人： Angela T. Hui , Mark S. Chang , Kuo-Tung Chang , Scott A. Bell
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.
摘要翻译：提供了一种用于形成集成电路系统的方法，包括在衬底上形成半导电层，形成间隔层叠层，其间隔填充物与半导体层相邻，间隙填料上形成层间电介质，形成过渡层该层在半导体层上具有凹陷并且与间隔物堆叠相邻，并且在凹部中形成金属层。

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