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11. 发明授权

US07492655B2 Memory device having high speed sense amplifier comprising pull-up circuit and pull-down circuits with drivability for each 失效
标题翻译：具有高速读出放大器的存储器件包括具有每个驱动能力的上拉电路和下拉电路
公开(公告)号：US07492655B2
公开(公告)日：2009-02-17
申请号：US11737693
申请日：2007-04-19
申请人： Satoru Akiyama , Riichiro Takemura , Takayuki Kawahara , Tomonori Sekiguchi
发明人： Satoru Akiyama , Riichiro Takemura , Takayuki Kawahara , Tomonori Sekiguchi
IPC分类号： G11C7/02
CPC分类号： G11C11/4091 , G11C7/065 , G11C2207/065 , H01L27/10897
摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
摘要翻译：构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于另一个下拉电路中的晶体管。首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

12. 发明授权

US07405588B2 Device and data processing method employing the device 失效
标题翻译：使用该设备的设备和数据处理方法
公开(公告)号：US07405588B2
公开(公告)日：2008-07-29
申请号：US10933272
申请日：2004-09-03
申请人： Takayuki Kawahara , Masayuki Miyazaki , Yasushi Goto , Natsuki Yokoyama , Takahiro Onai
发明人： Takayuki Kawahara , Masayuki Miyazaki , Yasushi Goto , Natsuki Yokoyama , Takahiro Onai
IPC分类号： H03K19/173
CPC分类号： G11C23/00 , H03K19/1776 , H03K19/1778
摘要： The present invention relates to an LSI in which functions can be changed, and realizes, particularly, a system LSI in which functions are changed by changing connections of the circuit by use of MEMS switches. A bistable MEMS switch which can maintain states, and exhibits optimal stitching property, i.e., the switch has a very small resistance of several Ω or less in an on-state, and has an infinite resistance in an off-state; is employed. An element in which functions can be changed during operation, is produced by utilizing a wiring layer of a CMOS semiconductor to form the MEMS switch. A semiconductor device exhibiting high-degree of freedom for changing functions, high-speed, and having small area, is realized.
摘要翻译：本发明涉及可以改变功能的LSI，特别是实现通过使用MEMS开关改变电路的连接来改变功能的系统LSI。可以保持状态并且表现出最佳缝合性能的双稳态MEMS开关，即开关在导通状态下具有几欧姆或更小的非常小的电阻，并且在断开状态下具有无限电阻; 被雇用。通过使用CMOS半导体的布线层来形成功能可以在操作期间改变的元件来形成MEMS开关。实现了具有高自由度，高速度，小面积化的高自由度的半导体装置。

13. 发明授权

US07338261B2 Hybrid compressor 有权
标题翻译：混合压缩机
公开(公告)号：US07338261B2
公开(公告)日：2008-03-04
申请号：US10797567
申请日：2004-03-11
申请人： Takayuki Kawahara , Hiromitsu Adachi , Shinichirou Wakou , Hideki Watanabe
发明人： Takayuki Kawahara , Hiromitsu Adachi , Shinichirou Wakou , Hideki Watanabe
IPC分类号： F04B9/14
CPC分类号： F04C29/005 , F04C18/0238 , F04C18/0269 , F04C23/001 , F04C23/008 , F04C29/0085 , F04C2240/45
摘要： A hybrid compressor includes a first compression mechanism, which is driven by a first drive source, and a second compression mechanism, which is driven by a second drive source, and a second radial axis of a second housing of the second compression mechanism is offset relative to a first radial axis of a first housing of the first compression mechanism, or a second diameter of the second housing of the second compression mechanism is less than a first diameter of the first housing of the first compression mechanism, or both. When a significant external force is applied to the front end of a vehicle containing the compressor, most of the external force may be absorbed by the first compression mechanism portion of the compressor, thereby reducing or avoiding damage to the second compression mechanism. In particular, when the second drive source is an incorporated electric motor, damage to the electric motor may be reduced or avoided.
摘要翻译：混合式压缩机包括由第一驱动源驱动的第一压缩机构和由第二驱动源驱动的第二压缩机构，并且第二压缩机构的第二壳体的第二径向轴线偏移相对到第一压缩机构的第一壳体的第一径向轴线，或者第二压缩机构的第二壳体的第二直径小于第一压缩机构的第一壳体的第一直径或两者。当对包含压缩机的车辆的前端施加显着的外力时，大部分外力可以被压缩机的第一压缩机构部分吸收，从而减少或避免对第二压缩机构的损坏。特别地，当第二驱动源是并入的电动机时，可以减少或避免对电动机的损坏。

14. 发明申请

US20070187736A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20070187736A1
公开(公告)日：2007-08-16
申请号：US11737693
申请日：2007-04-19
申请人： Satoru AKIYAMA , Riichiro Takemura , Takayuki Kawahara , Tomonori Sekiguchi
发明人： Satoru AKIYAMA , Riichiro Takemura , Takayuki Kawahara , Tomonori Sekiguchi
IPC分类号： H01L29/94
CPC分类号： G11C11/4091 , G11C7/065 , G11C2207/065 , H01L27/10897
摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
摘要翻译：构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于另一个下拉电路中的晶体管。首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

15. 发明授权

US07245532B2 Nonvolatile semiconductor memory device which stores multi-value information 失效
标题翻译：存储多值信息的非易失性半导体存储器件
公开(公告)号：US07245532B2
公开(公告)日：2007-07-17
申请号：US11332206
申请日：2006-01-17
申请人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
发明人： Yusuke Jyouno , Takayuki Kawahara , Katsutaka Kimura
IPC分类号： G11C10/00
CPC分类号： G11C11/005 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.
摘要翻译：为了使一个非易失性存储单元存储四值信息，在验证操作中，三种不同种类的阈值电压串行地施加到字线，以执行写入操作，控制存储器单元的阈值电压，并且两个与要写入的四值（2位）信息相对应的值（一位）信息由写数据转换电路合成，每次写入操作三次。以这种方式，将四值（2位）信息写入一个存储单元，并且可以增加存储单元的存储器容量。在信息读取操作中，将三种不同种类的电压施加到字线，所读出的三种二值（1位）信息由读取转换电路合成，存储器单元的存储器信息被转换到两位信息。

16. 发明申请

US20070076467A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070076467A1
公开(公告)日：2007-04-05
申请号：US11541542
申请日：2006-10-03
申请人： Masanao Yamaoka , Takayuki Kawahara
发明人： Masanao Yamaoka , Takayuki Kawahara
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode. Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area. Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.
摘要翻译：本发明的目的是提供一种降低使用按比例缩小的晶体管的整个低功耗SRAM LSI电路的功耗的技术，并且通过减少亚阈值泄漏电流来增加对存储单元的读和写操作的稳定性以及从漏极流到基板电极的漏电流。本发明的另一个目的是提供一种防止存储单元中的晶体管数量增加从而防止单元区域增加的技术。本发明的另一个目的是提供一种通过控制驱动晶体管的BOX层下的阱的电位来确保由具有BOX层的SOI或FD-SOI晶体管构成的SRAM存储单元的稳定工作的技术。

17. 发明申请

US20060146634A1 Semiconductor device 有权
公开(公告)号：US20060146634A1
公开(公告)日：2006-07-06
申请号：US11324357
申请日：2006-01-04
申请人： Kenichi Osada , Takayuki Kawahara
发明人： Kenichi Osada , Takayuki Kawahara
IPC分类号： G11C5/14 , G11C11/00
CPC分类号： G11C13/0004 , G11C5/147 , G11C8/08 , G11C13/0028 , G11C2213/79
摘要： To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output circuit, and to turn off the word line until the power supply circuit is activated. According to the present invention, unwanted current flow to the element can be prevented and thereby data destruction can be prevented.

18. 发明申请

US20050219935A1 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions 失效
公开(公告)号：US20050219935A1
公开(公告)日：2005-10-06
申请号：US11133232
申请日：2005-05-20
申请人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
发明人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
IPC分类号： G11C5/14 , G11C7/00 , G11C7/12 , G11C8/00 , G11C8/10 , G11C11/4094 , H03K5/08 , H03K17/00 , H03K17/693 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944
CPC分类号： G11C7/12 , G11C5/14 , G11C5/147 , G11C8/10 , G11C11/4094 , G11C11/413 , H03K5/08 , H03K17/693 , H03K19/00376 , H03K19/00384 , H03K19/017 , H03K19/01707 , H03K19/017518 , H03K19/09448 , H03K2217/0036
摘要： A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

19. 发明授权

US06950347B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06950347B2
公开(公告)日：2005-09-27
申请号：US10250922
申请日：2002-01-11
申请人： Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase
发明人： Hideaki Kurata , Naoki Kobayashi , Shunichi Saeki , Takashi Kobayashi , Takayuki Kawahara , Yoshinori Takase
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10 , G11C16/16 , G11C16/34 , H01L27/115
CPC分类号： G11C16/3409 , G11C11/5628 , G11C16/0425 , G11C16/0433 , G11C16/0466 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3436 , G11C16/3454 , G11C16/3459 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.
摘要翻译：本发明的非易失性存储器件通过将针对每个编程存储单元设置的特定电容中的电荷累积并且将经过该存储单元的电荷放电时产生的热电子注入到浮动栅极中来执行编程操作。因此，非易失性半导体存储器件的编程特性的变化减小，从而实现高速编程操作。

20. 发明授权

US06862220B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06862220B2
公开(公告)日：2005-03-01
申请号：US10886725
申请日：2004-07-09
申请人： Takayuki Kawahara , Nozomu Matsuzaki , Terumi Sawase , Masaharu Kubo
发明人： Takayuki Kawahara , Nozomu Matsuzaki , Terumi Sawase , Masaharu Kubo
IPC分类号： G11C16/04 , G06F15/78 , H01L21/28 , H01L21/82 , H01L21/8238 , H01L21/8247 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H03K19/173
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/0466 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42324 , H01L29/42332 , H01L29/7885
摘要： A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.
摘要翻译：包括安装在芯片上的非易失性存储单元和可变逻辑单元的半导体器件被配置为在较低电压下实现更高速度的操作。半导体器件包括：非易失性存储器单元，其包括多个可重写非易失性存储器单元，以及根据要加载到其存储单元中的逻辑构造定义数据确定其逻辑功能的可变逻辑单元。非易失性存储单元基本上具有由选择MOS晶体管和存储器MOS晶体管构成的分离栅极结构，并且被构造成使得选择MOS晶体管的栅极的介电耐受电压低于存储器MOS晶体管或栅极绝缘选择MOS晶体管的层比耐高压MOS晶体管薄。由于选择MOS晶体管具有高Gm，因此可以获得足够大的读取电流。

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