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11. 发明授权

US07031675B2 FM transmitter 失效
公开(公告)号：US07031675B2
公开(公告)日：2006-04-18
申请号：US10067234
申请日：2002-02-07
申请人： Masaru Kokubo
发明人： Masaru Kokubo
IPC分类号： H01Q11/12
CPC分类号： H04B1/04
摘要： An FM transmitter that can control start/idle of each of such devices as a buffer amplifier without using a sample-and-hold circuit for moving a PLL into open loop control, wherein a controller that controls a charging pump in the PLL to start/idle the FM modulation is controlled with use of a closed/open loop select signal of the PLL, a start/idle signal of the buffer amplifier, and a preamble detection signal. The power consumption of the FM transmission can be reduced, since both the buffer amplifier and the PLL in the FM transmitter can be started/idled together in a ganged manner.

12. 发明授权

US06731101B2 Modulation semiconductor integrated circuit device and testing method for oscillation circuit 失效
标题翻译：调制半导体集成电路器件及振荡电路的测试方法
公开(公告)号：US06731101B2
公开(公告)日：2004-05-04
申请号：US10086718
申请日：2002-03-04
申请人： Hirokazu Miyagawa , Katsumi Yamamoto , Tatsuji Matsuura , Masaru Kokubo
发明人： Hirokazu Miyagawa , Katsumi Yamamoto , Tatsuji Matsuura , Masaru Kokubo
IPC分类号： H03H1328
CPC分类号： H04B1/525 , H03B5/1215 , H03B5/1231 , H03B5/1243 , H04B1/52
摘要： In accomplishing an LC-oscillation VCO circuit which is immune to frequency deviation and a frequency-hopping radio communication apparatus using the VCO circuit, a modulation semiconductor integrated circuit device is designed to control the LC-oscillation VCO directly with data to be transmitted thereby implementing the modulation and switch the carrier frequency for frequency hopping. The integrated circuit device includes a current adjusting circuit which varies the current value of a D/A conversion circuit for producing a control voltage of VCO in accordance with the carrier frequency so that the variation of a modulation control voltage of VCO has a characteristic that is opposite to the characteristic of modulation frequency deviation, thereby nullifying the modulation frequency deviation of VCO.
摘要翻译：在实现对频率偏移免疫的LC振荡VCO电路和使用VCO电路的跳频无线电通信装置的情况下，调制半导体集成电路装置被设计成直接用要发送的数据来控制LC振荡VCO，从而实现调制和切换跳频的载波频率。集成电路装置包括电流调节电路，其根据载波频率改变用于产生VCO的控制电压的D / A转换电路的电流值，使得VCO的调制控制电压的变化具有与调制频率偏差的特性相反，从而使VCO的调制频率偏差无效。

13. 发明授权

US06594197B2 Semiconductor integrated circuit device 有权
公开(公告)号：US06594197B2
公开(公告)日：2003-07-15
申请号：US10185044
申请日：2002-07-01
申请人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
发明人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
IPC分类号： H03K300
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

14. 发明授权

US06215364B1 Variable frequency oscillator, and phase locked loop and clock synchronizer using thereof 有权
标题翻译：变频振荡器，以及使用其的锁相环和时钟同步器
公开(公告)号：US06215364B1
公开(公告)日：2001-04-10
申请号：US09288689
申请日：1999-04-09
申请人： Changku Hwang , Masaru Kokubo
发明人： Changku Hwang , Masaru Kokubo
IPC分类号： H03B502
CPC分类号： H03K3/0315 , H03L7/0893 , H03L7/0896 , H03L7/0995 , H03L7/10 , H03L2207/06
摘要： The variable frequency oscillator is capable of operation at a low power supply voltage and oscillating at a high frequency. A phase locked loop and a clock synchronizer use the variable frequency oscillator and have a wide oscillation frequency range. The variable frequency oscillator has plural delay cells which are cascaded and the output of the final stage delay cell is fed back to the input of the first stage delay cell. Each of the delay cells includes a differential amplifier and a positive feedback circuit, connected with input and output terminals intersecting with each other. The feedback circuit has complementary amplifiers each having an input terminal formed by connecting together gates of a pMOS and an nMOS transistor and an output terminal formed by connecting together the drains thereof. The positive feedback circuit, provided between output terminals of the differential amplifier, a controlling MOS transistor for inputting a frequency control signal for controlling the source current of the complementary amplifier to the gate thereof and the complementary amplifiers are connected in series between a power supply terminal and a ground terminal.
摘要翻译：变频振荡器能够在低电源电压下工作，并以高频振荡。锁相环和时钟同步器使用可变频率振荡器并具有宽的振荡频率范围。可变频率振荡器具有级联的多个延迟单元，并且最后级延迟单元的输出反馈到第一级延迟单元的输入。每个延迟单元包括差分放大器和正反馈电路，与彼此相交的输入和输出端子连接。反馈电路具有互补放大器，每个互补放大器具有通过将pMOS和nMOS晶体管的栅极连接在一起形成的输入端子和通过将其漏极连接而形成的输出端子。在差分放大器的输出端子之间设置的正反馈电路，用于输入用于控制互补放大器的源电流至其栅极的频率控制信号的控制MOS晶体管和互补放大器串联连接在电源端子和地面终端。

15. 发明授权

US07224948B1 Transmitter and radio communication terminal using the same 有权
标题翻译：发射机和无线电通信终端使用相同的
公开(公告)号：US07224948B1
公开(公告)日：2007-05-29
申请号：US10148960
申请日：2000-01-11
申请人： Taizo Yamawaki , Satoshi Tanaka , Masaru Kokubo , Kazuo Watanabe , Masumi Kasahara , Kazuaki Hori , Julian Hildersley
发明人： Taizo Yamawaki , Satoshi Tanaka , Masaru Kokubo , Kazuo Watanabe , Masumi Kasahara , Kazuaki Hori , Julian Hildersley
IPC分类号： H04B1/04 , H01Q11/12
CPC分类号： H03C3/0983 , H03C3/0925 , H03C3/0966 , H03D7/163 , H03J2200/17 , H03L7/23 , H04B1/0475 , H04B2001/0491 , H04L25/03343
摘要： There are provided a transmitter and a wireless communication terminal apparatus using the same for solving a problem of undesired spurs due to harmonics of an output signal of a frequency synthesizer, and further solving a problem of the undesired spurs occurring when the harmonics of an output signal of a crystal oscillator are mixed into a VCO to facilitate to design a circuit or a mounting substrate. The transmitter has a relationship between an output frequency of a PLL frequency conversion circuit (5) and output frequencies of frequency synthesizers (1, 2) stored therein, and the output frequencies of the frequency synthesizers (1, 2) input into the PLL frequency conversion circuit (5) are controlled on the basis of the relationship so that the undesired spurs are suppressed. Thereby, even when the undesired spurs occur in the output of the transmitter due to a crosstalk between circuits or through a substrate, which can be easily suppressed, it is therefore possible to reduce time and cost for redesigning the circuit or the substrate.
摘要翻译：提供了一种使用该发送器和无线通信终端装置的方法，用于解决由于频率合成器的输出信号的谐波引起的不期望的杂散问题，并且进一步解决了当输出信号的谐波发生时出现的不需要的杂散的问题的晶体振荡器混合到VCO中以便于设计电路或安装衬底。发射机具有PLL频率转换电路（5）的输出频率和存储在其中的频率合成器（1,2）的输出频率与输入到PLL频率的频率合成器（1,2）的输出频率之间的关系基于该关系来控制转换电路（5），从而抑制不需要的杂散。因此，即使由于电路之间的串扰或通过可以容易地抑制的基板而在发射机的输出端发生不想要的杂散，因此可以减少重新设计电路或基板的时间和成本。

16. 发明申请

US20070030079A1 Phase locked loop circuit and semiconductor integrated circuit device using the same 有权
标题翻译：锁相环电路和使用其的半导体集成电路器件
公开(公告)号：US20070030079A1
公开(公告)日：2007-02-08
申请号：US11488866
申请日：2006-07-19
申请人： Takashi Kawamoto , Masaru Kokubo
发明人： Takashi Kawamoto , Masaru Kokubo
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03L7/1976 , H03L2207/06
摘要： To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal. Also, the voltage controlled oscillator is capable of changing the frequency sensitivity of the output signal that is outputted with respect to the control voltage according to the trimming signal, and the upper limit frequency of the output signal according to the limit signal.
摘要翻译：提供能够执行不依赖于工艺变化和环境变化的满足期望特性的自动调整的锁相环电路。锁相环电路具有相位频率比较器，电荷泵，环路滤波器，分频器，选择器和压控振荡器。分频器输入输出信号和参考信号，分频输出信号，并输出反馈信号，并从输出信号输出选择信号，微调信号和限幅信号。压控振荡器输入控制电压，基极电压，微调信号和极限信号，根据控制电压改变输出信号频率，限制输出信号的上限频率。此外，压控振荡器能够根据微调信号和根据限制信号的输出信号的上限频率来改变与控制电压相关的输出信号的频率灵敏度。

17. 发明申请

US20050099289A1 Sensor with wireless communication function 失效
标题翻译：传感器具有无线通讯功能
公开(公告)号：US20050099289A1
公开(公告)日：2005-05-12
申请号：US10786542
申请日：2004-02-26
申请人： Hiroshi Arita , Masaru Kokubo , Kenichi Mizugaki
发明人： Hiroshi Arita , Masaru Kokubo , Kenichi Mizugaki
IPC分类号： H04M1/00 , G08B25/10 , H04M1/725 , H04M11/00 , G08B1/08
CPC分类号： G08B25/10
摘要： A sensor transmits and receives wireless signals at intervals. A sensor unit, a processor 130, a wireless transmitter circuit, and a wireless receiver circuit are activated in sequence only for a fixed time when the electric power generated by a generator circuit and charged in a capacitor reaches a preset level. Sensing information detected by the sensor unit is processed by the processor circuit and, information on the number of receivable bytes is added to the processing results in the wireless receiver circuit. This added information is sent as sensor information to the wireless host from the wireless transmitting circuit, and the wireless receiver circuit that activated after the wireless transmitter circuit was activated, receives a control information signal from the wireless host. This received information is processed in the processor circuit.
摘要翻译：传感器间隔地发送和接收无线信号。传感器单元，处理器130，无线发射器电路和无线接收器电路仅在发电机产生的电力并在电容器中充电的电力达到预设电平的固定时间内被依次激活。由传感器单元检测到的感测信息由处理器电路处理，并且关于可接收字节数的信息被添加到无线接收器电路中的处理结果。该添加的信息作为传感器信息从无线发送电路发送到无线主机，并且在无线发射机电路被激活之后激活的无线接收机电路从无线主机接收控制信息信号。该接收到的信息在处理器电路中被处理。

18. 发明授权

US06879188B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06879188B2
公开(公告)日：2005-04-12
申请号：US10322594
申请日：2002-12-19
申请人： Masayuki Miyazaki , Ken Tatezawa , Kiwamu Takada , Kunio Uchiyama , Osamu Nishii , Kiyoshi Hasegawa , Hirokazu Aoki , Masaru Kokubo
发明人： Masayuki Miyazaki , Ken Tatezawa , Kiwamu Takada , Kunio Uchiyama , Osamu Nishii , Kiyoshi Hasegawa , Hirokazu Aoki , Masaru Kokubo
IPC分类号： G06F1/04 , G06F1/06 , G06F1/32 , H01L21/82 , H01L21/822 , H01L27/04 , H03L7/07 , H03L7/081 , H03L7/099 , H03B19/00
CPC分类号： H03L7/07 , G06F1/04 , G06F1/3203 , H03L7/0812 , H03L7/0995 , Y02D10/126
摘要： A semiconductor integrated circuit device employing two clock signal generating circuits which output clock signals for distribution to an internal circuit of the device, the first and second clock signal generating circuits having different clock-settling times and the selection thereof is effected from outside of the device. A first one of the clock signal generating circuits uses, for example, a phase-locked loop circuit which has a large clock-settling time, and the second clock signal generating circuit is implemented, for example, using a delay-locked loop circuit whose clock-settling time is small, for example, 2-3 periods. Due to the selective actuation of the second clock signal generating circuit, which has a small clock-settling time, the generating of clock signals for the internal circuits can also be halted when the internal circuits of the device are halted thereby to further lower power consumption without compromising clock oscillator responsiveness.
摘要翻译：一种采用两个时钟信号发生电路的半导体集成电路器件，其输出时钟信号以分配到器件的内部电路，具有不同时钟稳定时间的第一和第二时钟信号发生电路及其选择是从器件外部实现的。时钟信号发生电路中的第一个使用例如具有大的时钟稳定时间的锁相环电路，并且第二时钟信号发生电路例如使用延迟锁定环电路来实现，时钟建立时间很小，例如2-3个周期。由于具有小的时钟建立时间的第二时钟信号产生电路的选择性致动，当器件的内部电路停止时也可以停止内部电路的时钟信号的产生，从而进一步降低功耗而不会影响时钟振荡器的响应。

19. 发明授权

US06870411B2 Phase synchronizing circuit 失效
标题翻译：相位同步电路
公开(公告)号：US06870411B2
公开(公告)日：2005-03-22
申请号：US10199068
申请日：2002-07-22
申请人： Yoshiyuki Shibahara , Masaru Kokubo
发明人： Yoshiyuki Shibahara , Masaru Kokubo
IPC分类号： H03L7/089 , H03L7/099 , H03L7/113 , H03L7/18 , H03L7/00
CPC分类号： H03L7/0995 , H03L7/0891 , H03L7/113 , H03L7/18
摘要： An object of this invention is to provide a phase synchronizing circuit capable of automatically adjusting a VCO such that the VCO satisfies a predetermined frequency range even in a frequency range in which the VCO oscillates by a leak current generated if a low threshold process is applied. The phase synchronizing circuit is composed of a PLL consisting of a phase comparator, a charge pump, a loop filter, a VCO, and a divider, and a calibration circuit for automatically adjusting a frequency range of the VCO. Before a convergence operation is started, a switch is closed in response to a signal Rst of the calibration circuit such that an output of the loop filter is leveled to the ground and the PLL is set to be an open loop. A VCO output Fo is set at an upper limit frequency or a lower limit frequency in response to a Vcal signal, and its frequency is measured by comparing its period with a period of a reference signal Fr, and signals Hb, Lb used for adjusting the frequency of the VCO are updated. The signals Hb, Lb are updated until the VCO satisfies the predetermined frequency range, and subsequently their values are maintained. The switch opens in response to the signal Rst, and the PLL is changed over to a close loop to start phase synchronization.
摘要翻译：本发明的目的是提供一种能够自动调节VCO的相位同步电路，使得即使在通过应用低阈值处理产生的泄漏电流在VCO振荡的频率范围内VCO也满足预定的频率范围。相位同步电路由包括相位比较器，电荷泵，环路滤波器，VCO和分频器的PLL构成，以及用于自动调整VCO的频率范围的校准电路。在开始收敛操作之前，响应于校准电路的信号Rst关闭开关，使得环路滤波器的输出被调平到地，并且PLL被设置为开环。 VCO输出Fo响应于Vcal信号被设置在上限频率或下限频率，并且通过将其周期与参考信号Fr的周期进行比较来测量其频率，并且用于调整信号的信号Hb，Lb 更新VCO的频率。信号Hb，Lb被更新，直到VCO满足预定的频率范围，并随后维持它们的值。响应于信号Rst，开关打开，PLL被切换到闭环以开始相位同步。

20. 发明授权

US06515519B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06515519B1
公开(公告)日：2003-02-04
申请号：US09580646
申请日：2000-05-30
申请人： Masayuki Miyazaki , Ken Tatezawa , Kiwamu Takada , Kunio Uchiyama , Osamu Nishii , Kiyoshi Hasegawa , Hirokazu Aoki , Masaru Kokubo
发明人： Masayuki Miyazaki , Ken Tatezawa , Kiwamu Takada , Kunio Uchiyama , Osamu Nishii , Kiyoshi Hasegawa , Hirokazu Aoki , Masaru Kokubo
IPC分类号： H03B1900
CPC分类号： H03L7/07 , G06F1/04 , G06F1/3203 , H03L7/0812 , H03L7/0995 , Y02D10/126
摘要： A signal from a crystal resonator or an external clock signal are input from terminals xta1 or exta1, and the signal from the crystal resonator or external clock signal are selected by mode terminal mod8 and input to an oscillator OSC. An input clock signal ckl1 is frequency-divided to desired values by a divider DIV1. A divided clock signal clk2 is input as the reference clock of a phase-locked loop PLL1 or delay-locked loop DLL1, and a clock signal output by a circuit selected by a selector SEL3 passes via a divider DIV2 to be distributed to an LSI. The phase-locked loop PLL1 has a clock settling time of at least 40 clock periods, whereas the clock settling time of the delay-locked loop DLL1 is 2-3 periods.
摘要翻译：来自晶体谐振器或外部时钟信号的信号从端子xta1或exta1输入，并且来自晶体谐振器或外部时钟信号的信号由模式端子mod8选择并输入到振荡器OSC。输入时钟信号ck11由分频器DIV1分频为期望值。输入分频时钟信号clk2作为锁相环路PLL1或延迟锁定环路DLL1的基准时钟，由选择器SEL3选择的电路输出的时钟信号通过分配器DIV2通过分配给LSI。锁相环PLL1具有至少40个时钟周期的时钟建立时间，而延迟锁定环DLL1的时钟建立时间为2-3个周期。

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