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11. 发明授权

US08427865B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08427865B2
公开(公告)日：2013-04-23
申请号：US13440225
申请日：2012-04-05
申请人： Akio Shima , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
发明人： Akio Shima , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
IPC分类号： G11C11/00 , H01L29/80
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
摘要翻译：提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以构成三维存储器单元格阵列。存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

12. 发明申请

US20100182828A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20100182828A1
公开(公告)日：2010-07-22
申请号：US12688886
申请日：2010-01-17
申请人： Akio SHIMA , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
发明人： Akio SHIMA , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
IPC分类号： G11C11/00 , H01L47/00 , G11C8/00
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
摘要翻译：提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以构成三维存储器单元格阵列。存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

13. 发明授权

US08169819B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08169819B2
公开(公告)日：2012-05-01
申请号：US12688886
申请日：2010-01-17
申请人： Akio Shima , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
发明人： Akio Shima , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
IPC分类号： G11C11/00 , H01L29/80
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
摘要翻译：提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以配置三维存储器单元格阵列。存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

14. 发明申请

US20120211718A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20120211718A1
公开(公告)日：2012-08-23
申请号：US13440225
申请日：2012-04-05
申请人： AKIO SHIMA , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
发明人： AKIO SHIMA , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
IPC分类号： H01L45/00
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
摘要翻译：提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以配置三维存储器单元格阵列。存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

15. 发明授权

US07638786B2 Semiconductor and semiconductor manufacturing arrangements having a chalcogenide layer formed of columnar crystal grains perpendicular to a main substrate surface 有权
标题翻译：具有由垂直于主衬底表面的柱状晶粒形成的硫族化物层的半导体和半导体制造布置
公开(公告)号：US07638786B2
公开(公告)日：2009-12-29
申请号：US11272811
申请日：2005-11-15
申请人： Yuichi Matsui , Motoyasu Terao , Norikatsu Takaura , Takahiro Morikawa , Naoki Yamamoto
发明人： Yuichi Matsui , Motoyasu Terao , Norikatsu Takaura , Takahiro Morikawa , Naoki Yamamoto
IPC分类号： H01L29/02
CPC分类号： C23C14/5806 , C23C14/0623 , C23C14/541 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/144 , H01L45/1625 , H01L45/1641
摘要： The annealing process at 400° C. or more required for the wiring process for a phase change memory has posed the problem in that the crystal grains in a chalcogenide material grow in an oblique direction to cause voids in a storage layer. The voids, in turn, cause peeling due to a decrease in adhesion, variations in resistance due to improper contact with a plug, and other undesirable events. After the chalcogenide material has been formed in an amorphous phase, post-annealing is conducted to form a (111)-oriented and columnarly structured face-centered cubic. This is further followed by high-temperature annealing to form a columnar, hexagonal closest-packed crystal. Use of this procedure makes it possible to suppress the growth of inclined crystal grains that causes voids, since crystal grains are formed in a direction perpendicular to the surface of an associated substrate.
摘要翻译：在相变存储器的布线处理所需的400℃以上所需的退火处理的问题在于，硫属化物材料中的晶粒沿倾斜方向生长，从而在储存层中产生空隙。这些空隙又由于粘合力的降低而导致剥离，由于与插头的不正确接触导致的电阻变化以及其它不期望的事件。在非晶态形成硫族化物材料之后，进行后退火以形成（111）取向和柱状结构的面心立方。此后进一步进行高温退火以形成柱状，六边形最接近填充的晶体。使用该方法可以抑制由于在垂直于相关衬底的表面的方向上形成晶粒而导致空隙的倾斜晶粒的生长。

16. 发明申请

US20060105556A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060105556A1
公开(公告)日：2006-05-18
申请号：US11272811
申请日：2005-11-15
申请人： Yuichi Matsui , Motoyasu Terao , Norikatsu Takaura , Takahiro Morikawa , Naoki Yamamoto
发明人： Yuichi Matsui , Motoyasu Terao , Norikatsu Takaura , Takahiro Morikawa , Naoki Yamamoto
IPC分类号： H01L21/20
CPC分类号： C23C14/5806 , C23C14/0623 , C23C14/541 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/144 , H01L45/1625 , H01L45/1641
摘要： The annealing process at 400° C. or more required for the wiring process for a phase change memory has posed the problem in that the crystal grains in a chalcogenide material grow in an oblique direction to cause voids in a storage layer. The voids, in turn, cause peeling due to a decrease in adhesion, variations in resistance due to improper contact with a plug, and other undesirable events. After the chalcogenide material has been formed in an amorphous phase, post-annealing is conducted to form a (111)-oriented and columnarly structured face-centered cubic. This is further followed by high-temperature annealing to form a columnar, hexagonal closest-packed crystal. Use of this procedure makes it possible to suppress the growth of inclined crystal grains that causes voids, since crystal grains are formed in a direction perpendicular to the surface of an associated substrate.
摘要翻译：在相变存储器的布线处理所需的400℃以上所需的退火处理的问题在于，硫属化物材料中的晶粒沿倾斜方向生长，从而在储存层中产生空隙。这些空隙又由于粘合力的降低而导致剥离，由于与插头的不正确接触导致的电阻变化以及其它不期望的事件。在非晶态形成硫族化物材料之后，进行后退火以形成（111）取向和柱状结构的面心立方。此后进一步进行高温退火以形成柱状，六边形最接近填充的晶体。使用该方法可以抑制由于在垂直于相关衬底的表面的方向上形成晶粒而导致空隙的倾斜晶粒的生长。

17. 发明授权

US5898829A Fault-tolerant computer system capable of preventing acquisition of an input/output information path by a processor in which a failure occurs 失效
标题翻译：容错计算机系统能够防止由发生故障的处理器获取输入/输出信息路径
公开(公告)号：US5898829A
公开(公告)日：1999-04-27
申请号：US757564
申请日：1996-11-27
申请人： Takahiro Morikawa
发明人： Takahiro Morikawa
IPC分类号： G05B9/03 , G06F11/00 , G06F11/20 , G06F15/16 , G06F15/177
CPC分类号： G06F11/2028 , G05B9/03 , G06F11/0724 , G06F11/0796 , G06F11/2033 , G06F11/2038 , G06F11/2041 , G06F11/0757
摘要： In a computer system comprising first through N-th processors which are provided with first through N-th processor input/output information transmission paths, respectively, an n-th processor is connected to an (n-1)-th processor, an (n-2)-th processor, an (n+1)-th processor, and an (n+2)-th processor, where n represents each of 1 through N, both inclusive. Coupled to the first through the N-th processor input/output information transmission paths and to a system input/output information transmission path for a controlled system, an input/output information path control device connects the system input/output information transmission path to one of the first through the N-th processor input/output information transmission paths. The n-th processor comprises an n-th central processing unit (CPU) for managing the whole of the (n-1)-th processor, an n-th failure detecting circuit for always monitoring an operation state in the (n-1)-th processor, and an n-th input/output information transmission path acquisition control circuit for directing control operation for the input/output information transmission path control device.
摘要翻译：在包括分别具有第一至第N处理器输入/输出信息传输路径的第一至第N处理器的计算机系统中，第n处理器分别连接到第（n-1）个处理器，（ n-2）处理器，第（n + 1）处理器和第（n + 2）处理器，其中n表示1到N中的每一个。耦合到第一至第N处理器输入/输出信息传输路径以及受控系统的系统输入/输出信息传输路径，输入/输出信息路径控制装置将系统输入/输出信息传输路径连接到一个通过第N个处理器输入/输出信息传输路径。第n个处理器包括用于管理整个第（n-1）个处理器的第n个中央处理单元（CPU），第n个故障检测电路，用于始终监视第（n-1）个处理器中的操作状态以及用于引导输入/输出信息传输路径控制装置的控制操作的第n输入/输出信息传输路径获取控制电路。

18. 发明授权

US08735865B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08735865B2
公开(公告)日：2014-05-27
申请号：US12987109
申请日：2011-01-08
申请人： Hiroyuki Minemura , Yumiko Anzai , Takahiro Morikawa , Toshimichi Shintani , Yoshitaka Sasago
发明人： Hiroyuki Minemura , Yumiko Anzai , Takahiro Morikawa , Toshimichi Shintani , Yoshitaka Sasago
IPC分类号： H01L29/02 , H01L29/06 , G11C11/00
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/0069 , G11C2013/008 , G11C2213/71 , G11C2213/75 , H01L27/2409 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/1286 , H01L45/1293 , H01L45/144
摘要： For decreasing a recording current and suppressing a cross erase simultaneously, a three-dimensional phase-change memory for attaining higher sensitivity and higher reliability by the provision of a chalcogenide type interface layer is provided, in which an electric resistivity, a thermal conductivity, and a melting point of the material of the interface layer are selected appropriately, thereby improving the current concentration to the phase-change material and thermal and material insulation property with Si channel upon writing.
摘要翻译：为了同时降低记录电流和抑制交叉擦除，提供了一种用于通过提供硫族化物型界面层来获得更高灵敏度和更高可靠性的三维相变存储器，其中电阻率，热导率和适当地选择界面层的材料的熔点，从而提高相变材料的电流浓度和写入时Si通道的热和材料绝缘性能。

19. 发明申请

US20130234101A1 NON-VOLATILE MEMORY DEVICE AND PRODUCTION METHOD THEREOF 有权
公开(公告)号：US20130234101A1
公开(公告)日：2013-09-12
申请号：US13884331
申请日：2010-11-22
申请人： Yoshitaka Sasago , Masaharu Kinoshita , Takahiro Morikawa , Akio Shima , Takashi Kobayashi
发明人： Yoshitaka Sasago , Masaharu Kinoshita , Takahiro Morikawa , Akio Shima , Takashi Kobayashi
IPC分类号： H01L45/00
CPC分类号： H01L27/2436 , H01L27/1157 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/66833 , H01L29/7926 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1616 , H01L45/1683
摘要： A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.

20. 发明申请

US20130048938A1 PHASE CHANGE MEMORY DEVICE 有权
标题翻译：相变存储器件
公开(公告)号：US20130048938A1
公开(公告)日：2013-02-28
申请号：US13589457
申请日：2012-08-20
申请人： Toshimichi Shintani , Takahiro Morikawa , Takahiro Odaka
发明人： Toshimichi Shintani , Takahiro Morikawa , Takahiro Odaka
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L27/2454 , H01L27/2481 , H01L45/124 , H01L45/144 , H01L45/1691
摘要： An object of the present invention is to provide a technique for suppressing thermal disturbance of a phase change memory device having a three-dimensional structure. In the phase change memory device having a three-dimensional structure, a material having a high thermal conductivity is used as a gate insulation film of a MOS transistor for selection, and causes heat transmitted to a Si channel layer from a phase change recording film to successfully diffuse to a gate electrode. In this way, since heat generated from a recording bit diffuses to a non-selected bit adjacent to it, it is possible to suppress thermal disturbance. BN, Al2O3, AlN, TiO2, Si3N4, ZnO and the like are useful as a gate insulation film having a high thermal conductivity.
摘要翻译：本发明的目的是提供一种用于抑制具有三维结构的相变存储装置的热扰动的技术。在具有三维结构的相变存储器件中，使用具有高热导率的材料作为用于选择的MOS晶体管的栅极绝缘膜，并且将从相变记录膜传输到Si沟道层的热量成功地扩散到栅电极。以这种方式，由于从记录位产生的热扩散到与其相邻的非选择位，因此可以抑制热扰动。 BN，Al 2 O 3，AlN，TiO 2，Si 3 N 4，ZnO等可以用作具有高导热性的栅极绝缘膜。

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